Memory ECC Using P-Adic Lee Codes for Burst Error Correction
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Solution Overview
Problem
Conventional error correction systems in high-density memory systems struggle to effectively handle both random and burst errors, particularly in three-dimensionally structured memory cells, where existing ECC systems like RS-ECC and BCH-ECC face challenges in processing time and circuit complexity, especially with increasing data batch sizes.
Innovation Solution
The implementation of a p-LM-ECC system using a Lee Metric Code in a Galois field of prime p, which converts binary data into p-adic data words, generates a Lee metric code capable of correcting both random and burst errors by employing a syndrome-based error correction process that reduces computational complexity and circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC systems (RS-ECC or BCH-ECC) are used to correct errors in high-density memory, then error correction capability is provided, but processing time increases and circuit complexity increases
Solution Approach 1:
The patent changes the mathematical field parameter from GF(2^m) to GF(p) where p is a prime number. This parameter change fundamentally alters the error correction approach, enabling simpler circuit implementation while maintaining correction capability for both random and burst errors. The use of p-adic number system and Lee metric code transforms the complex polynomial operations into simpler modular arithmetic operations.
Solution Approach 2:
The patent segments the error correction process into distinct functional units: syndrome calculation unit, error detection unit, and error correction unit. Each unit performs a specific function with simplified logic, avoiding the need for complex polynomial division and multiplication operations required by conventional RS-ECC and BCH-ECC systems.
2Reliability
If conventional ECC systems are used to correct errors in high-density memory, then error correction capability is provided, but processing time increases
Solution Approach 1:
The patent changes the mathematical field parameter from GF(2^m) to GF(p) where p is a prime number. This parameter change fundamentally alters the error correction approach, enabling simpler circuit implementation while maintaining correction capability for both random and burst errors. The use of p-adic number system and Lee metric code transforms the complex polynomial operations into simpler modular arithmetic operations.
Solution Approach 2:
The patent performs preliminary syndrome calculation during the write operation, storing the syndrome information alongside the data in the memory. During read operations, the syndrome is readily available for immediate error detection and correction, eliminating the need for time-consuming re-calculation and enabling faster error handling.
3Quantity of substance
If memory capacity is increased with fine fabrication and three-dimensional structures, then storage density is improved, but error occurrence rate increases
Solution Approach 1:
The patent applies local quality by treating different types of errors (random errors and burst errors) with specialized detection and correction mechanisms. The error correction unit identifies whether errors are random or burst-based and applies appropriate correction strategies, providing targeted protection for different error patterns that occur in high-density memory structures.
Solution Approach 2:
The patent uses a composite error correction approach combining Lee metric code with p-adic number system. This composite mathematical framework integrates the advantages of both systems: the burst error correction capability of Lee metric and the algebraic structure of p-adic numbers, creating a robust error correction mechanism suitable for high-density memory with multiple error types.
Data Source
AI summary
A memory system according to the embodiment comprises a p-adic number converter unit operative to convert δ-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D.


