Semiconductor Memory ECC Efficiency via Page Segmentation
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in accurately storing and retrieving multilevel data due to variations in threshold voltage levels, leading to increased defect percentages across different pages, which affects the efficiency of Error-Correcting Code (ECC) units when data is written or read page by page.
Innovation Solution
A semiconductor memory device is designed with multiple memory cells and data storage circuits that allow for the selection and storage of data bit by bit across multiple pages, enabling simultaneous writing and reading of data across these pages, thereby improving ECC efficiency by distributing data uniformly across the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is written or read page by page in conventional NAND flash memory, then the memory can operate with standard page-based interfaces, but the ECC efficiency decreases due to increased defect percentages across different pages
Solution Approach 1:
The patent segments the memory cell array into multiple ECC units, where each ECC unit contains multiple pages. This segmentation allows the ECC to process data across multiple pages simultaneously, improving ECC efficiency while maintaining page-based access operations. The control circuit is divided into multiple units, each responsible for specific ECC units, enabling parallel processing.
Solution Approach 2:
The patent merges multiple pages into a single ECC unit, combining the data from multiple pages to be processed together by the ECC circuit. This merging approach increases the amount of data that can be corrected per ECC operation, thereby improving overall ECC efficiency without requiring separate operations for each page.
2Quantity of substance
If multilevel data is stored in a single memory cell to increase storage capacity, then storage density improves, but threshold voltage variations increase leading to higher defect percentages
Solution Approach 1:
The patent applies local quality by organizing memory cells into specific ECC units with controlled characteristics. Each ECC unit is designed to have uniform defect percentages across its pages, creating localized regions with optimized properties for ECC processing. This allows the system to maintain high storage capacity through multilevel cells while ensuring reliable data retrieval through carefully constructed ECC units with consistent quality characteristics.
Data Source
AI summary
Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.