Memory Controller ECC Parallel Decoding for DRAM Error Correction

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Solution Overview

Problem

Existing memory systems face challenges in efficiently correcting errors, particularly symbol, multi-bit, and triple-bit errors, in volatile memory devices like DRAM, which affect data integrity and reliability.

Innovation Solution

A memory controller and system that incorporates an error correction code (ECC) engine with parallel first and second ECC decodings using sub check matrices to correct symbol and multi-bit errors, and detect triple-bit errors, reducing decoding latency and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a single ECC decoding process is used to correct errors in memory modules, then the decoding complexity is manageable, but the decoding latency increases and error correction efficiency is reduced

Engineering Contradiction:
Improvedecoding latencyVSAvoidECC decoding complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides the ECC decoding process into two parallel decoding operations: first ECC decoding (symbol error correction) and second ECC decoding (multi-bit error correction and triple-bit error detection). By segmenting the decoding tasks and executing them simultaneously using different sub-check matrices, the system reduces overall decoding latency while distributing computational complexity across multiple specialized decoding paths.

Inventive Principle:
Principle #1Segmentation

2Productivity

If parallel first and second ECC decodings are performed to correct symbol errors and multi-bit errors simultaneously, then error correction efficiency improves, but the ECC decoding complexity increases

Engineering Contradiction:
Improveerror correction efficiencyVSAvoidECC decoding complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments error correction into two specialized decoding paths: first ECC decoding for symbol errors and second ECC decoding for multi-bit errors. Each decoding path uses optimized sub-check matrices tailored to specific error types, enabling parallel execution and improving overall correction efficiency while managing complexity through functional specialization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ECC engine is designed with multi-functionality to perform both first ECC decoding (symbol error correction) and second ECC decoding (multi-bit error correction and triple-bit error detection) within a unified architecture. This universal design allows the system to handle multiple error types simultaneously through parallel decoding operations, improving productivity while consolidating complexity into a single multi-capable engine.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If comprehensive error detection and correction is implemented for symbol, multi-bit, and triple-bit errors, then data integrity improves, but the decoding process becomes more complex and time-consuming

Engineering Contradiction:
Improvedata integrityVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements comprehensive error detection and correction by segmenting the decoding process into two parallel paths: first ECC decoding that corrects symbol errors and second ECC decoding that corrects multi-bit errors and detects triple-bit errors. This segmentation enables simultaneous handling of multiple error types, improving data integrity while reducing total decoding time through parallel execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary error classification and routing before full decoding by generating syndromes and determining which decoding path (first or second ECC decoding) is needed based on error patterns. This preliminary action enables the system to prepare and execute the appropriate decoding operation in advance, reducing actual decoding time while maintaining comprehensive error detection and correction capabilities for high reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12547494B2Memory controllers and memory systems
Publication Date: 2026.02.10 SAMSUNG ELECTRONICS CO LTD
  • US12547494B2 patent drawing
  • US12547494B2 patent drawing
  • US12547494B2 patent drawing

AI summary

A memory controller to control a memory module including data chips and a parity chip, includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder to perform a first ECC decoding to correct a symbol error in a read codeword set and perform a second ECC decoding to correct multi-bit error and to detect triple-bit error in the read codeword set in parallel with performing the first ECC decoding. The ECC decoder generates a syndrome including a first sub syndrome, a second sub syndrome and a third sub syndrome, corrects the symbol error, and corrects the multi-bit error and detect the triple bit error.