Memory Bank ECC Bus Layout for Parallel Mask Writes
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Solution Overview
Problem
Existing semiconductor memory devices with error check and correct (ECC) functions face performance deterioration when multiple mask write processes are executed on the same banks due to sequential execution requirements, leading to inefficiencies in data processing.
Innovation Solution
The semiconductor memory device incorporates a first bus connecting sense amplifiers and error correction units, and a second bus connecting ECC code generation units and sense amplifiers, allowing parallel data output and input operations within the same bank, even when accessing the same banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mask write processes are executed on the same banks sequentially, then data accuracy is maintained through proper error correction, but data processing speed deteriorates due to waiting for previous processes to complete
Solution Approach 1:
The patent segments the data processing path into two independent parallel paths: one path handles data reading and error correction (via the first bus connecting sense amplifier to error correction unit), while the other path handles ECC code generation (via the second bus connecting ECC code generation unit to sense amplifier). This segmentation allows multiple mask write processes to execute simultaneously on the same banks without sequential waiting, maintaining data accuracy through proper error correction while significantly improving processing speed.
2Productivity
If parallel execution of mask write processes is implemented, then data processing efficiency improves, but system complexity increases due to additional bus structures
Solution Approach 1:
The patent implements multi-functionality by having the sense amplifier serve multiple purposes simultaneously: it can read data for error correction processing while also receiving newly generated ECC codes for writing. The first bus and second bus provide universal data transmission pathways that handle both error correction data flow and ECC code generation data flow, enabling parallel execution of multiple mask write processes without requiring completely separate dedicated structures for each function, thus improving productivity while controlling system complexity.
Data Source
AI summary
A semiconductor memory device includes a plurality of banks, a sense amplifier, an ECC code generation unit, an error correction unit, a first bus, and a second bus. The banks include a data recording unit in which rewritten data is to be written, and an ECC code recording unit in which an error correction code corresponding to the rewritten data is to be written. The sense amplifier is included in each of the banks and configured to read and write data from and to each of the banks. The ECC code generation unit generates the error correction code. The error correction unit corrects an error of data using the error correction code. The first bus connects the sense amplifier in each of the banks and the error correction unit. The second bus connects the ECC code generation unit and the sense amplifier in each of the banks.