Memory ECC Test Modes for Direct Parity Array Access
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Solution Overview
Problem
The existing methods for testing on-die error checking and correction (ECC) function in memory devices like LPDDR4x and DDR5 DRAM lack effective testing methodologies, posing risks to yield and manufacturing costs.
Innovation Solution
A memory device with an ECC circuit coupled to a data array and a parity array, featuring three test modes: disabling ECC function, direct access to parity array for reading/writing, and generating parity information to test circuit components, ensuring comprehensive ECC function verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC function is integrated into normal memory operations, then memory reliability is improved, but testing complexity increases and yield risk increases
Solution Approach 1:
The patent segments the ECC testing process into distinct test modes (first test mode and second test mode) that can be independently activated. The ECC circuit is separated from normal memory operations during testing, allowing independent verification of ECC functionality without interfering with standard memory tests.
Solution Approach 2:
The patent extracts the ECC circuit functionality from normal memory operations during testing. By providing a dedicated test mode where ECC operations can be independently activated and tested separately from regular memory read/write operations, the testing complexity is managed while maintaining reliability benefits.
2Reliability
If ECC circuit is added to memory device, then error correction capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements multi-functionality in the ECC circuit by enabling it to operate in both normal memory mode (providing error correction) and dedicated test mode (enabling comprehensive ECC verification). This universal design allows the same hardware to serve multiple purposes, reducing the need for additional dedicated test hardware and thereby controlling manufacturing costs.
Solution Approach 2:
The ECC circuit performs self-testing through the dedicated test modes. By enabling the ECC circuit to test its own functionality alongside normal memory operations, the patent eliminates the need for complex external test equipment, reducing manufacturing costs while maintaining error correction capability.
3Measurement precision
If dedicated ECC test mode is provided, then testing completeness is improved, but device operation complexity increases
Solution Approach 1:
The patent implements dynamic operation modes that allow the memory device to switch between normal operation and dedicated ECC test modes. The control logic dynamically activates appropriate test sequences based on mode signals, providing comprehensive testing when needed while maintaining simple normal operation, thus balancing testing completeness with ease of operation.
Solution Approach 2:
The patent incorporates periodic test sequences within the dedicated ECC test mode, where specific test patterns are applied at regular intervals to verify ECC functionality. This periodic approach ensures thorough testing coverage while maintaining clear, structured operation that doesn't overly complicate device usage.
Data Source
AI summary
A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.