Memory Device ECC Architecture with Adaptive Parity Allocation
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Solution Overview
Problem
Memory devices face excessive power consumption due to fixed and high ECC correction power usage throughout their life cycle, which is not optimized for varying Bit Error Rates (BER) caused by factors like manufacturing quality, environmental conditions, and usage.
Innovation Solution
An adaptive ECC architecture that dynamically adjusts ECC protection levels based on the health status of memory cells, using a variable number of parity cells for error correction, reallocating unused parity cells for extra payload storage when lower ECC protection is needed, and increasing parity cells for higher protection when BER increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed high ECC correction power is used throughout the memory device life cycle, then reliability is maintained, but power consumption is excessive
Solution Approach 1:
The ECC correction power is made dynamic rather than fixed. The system adjusts the number of parity bits and ECC correction capability based on the current health status and Bit Error Rate of the memory device, allowing the error correction power to vary over time according to actual needs, thus reducing unnecessary power consumption while maintaining reliability
Solution Approach 2:
The system changes the parameter of ECC correction capability based on memory device status. By monitoring parameters such as Bit Error Rate and health status, the system adjusts the number of parity bits and ECC correction level, transitioning between different correction power states to optimize the balance between reliability and power consumption
2Reliability
If maximum ECC protection level is used, then error correction capability is maximized, but memory capacity is reduced due to more parity cells
Solution Approach 1:
The allocation of parity cells is made dynamic. The system adjusts the number of parity bits based on the current error rate and health status of the memory device. When the device is healthy, fewer parity bits are used, freeing up memory capacity. When errors increase, the system dynamically allocates more parity bits to maintain reliability, thus optimizing the trade-off between error correction capability and available memory capacity
Solution Approach 2:
The system changes the parameter of parity bit allocation based on monitored performance metrics. By adjusting the number of parity bits according to Bit Error Rate and health status, the system dynamically optimizes the balance between error correction capability and usable memory capacity, avoiding the need to always allocate maximum parity bits
3Reliability
If ECC is calibrated on end-of-life reliability, then worst-case error correction is ensured, but power consumption is excessive during early life when BER is lower
Solution Approach 1:
The system implements periodic monitoring of memory device health status and Bit Error Rate, and adjusts ECC correction power accordingly. Instead of using fixed maximum correction power throughout the device life, the system periodically evaluates actual error rates and adjusts the number of parity bits and correction capability, reducing power consumption during early life when BER is lower while ensuring adequate protection when needed
Solution Approach 2:
The system uses feedback from health status monitoring and Bit Error Rate measurement to adjust ECC correction power. By continuously monitoring device performance and feeding this information back to the ECC controller, the system dynamically adjusts the number of parity bits and correction capability, ensuring end-of-life reliability while avoiding excessive power consumption during early life when actual error rates are lower
Data Source
AI summary
The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.