Memory ECC Circuit Selectable Parity Expansion
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Solution Overview
Problem
Semiconductor memory devices face a trade-off between error correction capability and storage space due to the use of parity bits, limiting the ability to detect and correct errors effectively.
Innovation Solution
The implementation of a memory device with a mode register that allows users to selectively generate additional parity bits beyond the default, enabling a two-pass write and read operation to store and retrieve these extra bits, enhancing error correction capabilities from single error correction to double error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional parity bits are generated beyond the default number, then error correction capability is improved (from single error correction to double error detection), but storage space is reduced
Solution Approach 1:
The patent implements dynamic error correction capability by allowing the memory device to be configured with different numbers of parity bits through a mode register. Users can select between default parity configuration and expanded parity configuration, enabling the system to adapt its error correction capability (from single error correction to double error detection) based on reliability requirements while managing storage space accordingly.
Solution Approach 2:
The patent changes the parameter of parity bit quantity from a fixed default value to a variable that can be expanded. By generating an expanded set of parity bits that includes the default parity bits plus additional parity bits, the system adjusts the error correction parameter to achieve enhanced reliability (double error detection) while being aware of the storage space trade-off.
2Reliability
If more parity bits are used to enhance error detection and correction, then data protection is improved, but the amount of storage available in the array is reduced
Solution Approach 1:
The system provides dynamic data protection by enabling users to configure the memory device with expanded parity bits when enhanced protection is needed. The mode register allows switching between standard and expanded error correction modes, making data protection adaptable to different operational requirements while clearly showing the storage area trade-off.
Solution Approach 2:
The patent changes the parity bit parameter from a fixed value to an expandable configuration. By generating additional parity bits beyond the default set, the system increases the data protection parameter (enabling double error detection) while the user can assess and manage the corresponding reduction in available storage area.
Data Source
AI summary
Apparatuses, systems, and methods for selectable expansion of error correction capability. A memory includes an error correction code (ECC) circuit which generates a default number of parity bits based on written data, and uses those parity bits to correct error(s) in the data. A setting of the memory may specify some number of extra bits of parity. When enabled the ECC circuit may generate parity include the default parity and the extra parity. The default parity is stored in an ECC column plane. The extra parity is stored in the data column planes. When the extra parity is enabled, the ECC circuit may detect/correct more bits of error in the data.