Memory Device ECC Circuit Parity Bit Region Reduction
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Solution Overview
Problem
As the amount of data stored in memory devices increases, the number of required parity data bits for error checking and correction also increases, leading to a significant increase in the size of the memory device due to the considerable occupation area of the parity bit region, which is inefficient.
Innovation Solution
A method of operating a memory device that reduces the parity bit region by reading and writing data using a command and address from a memory controller, where a read code word including data and parity data is read, and corrected data is generated using an ECC circuit, allowing for a fixed size of the read code word regardless of the operation mode, thereby optimizing the use of memory cell array space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the amount of data stored in the memory device is increased, then the data storage capacity is improved, but the number of required parity data bits increases leading to increased memory device size
Solution Approach 1:
The patent merges data from multiple addresses (first address and second address) into a single read code word that is processed together by the ECC circuit. This allows the parity bits to protect combined data from multiple locations, reducing the total number of parity bits needed compared to protecting each location separately.
Solution Approach 2:
The ECC circuit is designed to handle multiple data sources universally - it can process data from a single address or combine data from multiple addresses (first address and second address) into one code word. This multi-functional approach allows flexible error protection with reduced overhead.
2Reliability
If the number of parity data bits is increased to correct errors, then the error correction capability is improved, but the occupation area of the parity bit region increases
Solution Approach 1:
The patent combines data from multiple addresses into a single code word that shares common parity bits. The ECC circuit generates parity bits for the combined code word rather than generating separate parity bits for each address, reducing the total parity bit region area while maintaining error correction capability.
Solution Approach 2:
The patent changes the structure of the code word by incorporating data from multiple addresses (first address and second address) into a unified code word format. This parameter change in code word composition allows more efficient use of parity bits across multiple data locations.
Data Source
AI summary
In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.