Memory Device Parallel Testing with ECC Parity Storage
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Solution Overview
Problem
Memory devices employing on-chip error correction code (ECC) schemes face challenges in parallel testing due to the inability to write and read test data simultaneously across normal and ECC memory cells, as parity bits for error correction are stored in separate regions, hindering traditional parallel bit test (PBT) methods.
Innovation Solution
A method involving a temporary storage circuit for parity bits, allowing for separate write and read operations across normal and parity cell regions, with error correction using the stored parity bits to output error-corrected test data, enabling parallel testing of memory devices with on-chip ECC schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional parallel bit test (PBT) is used to test memory devices, then test time is reduced through parallel testing, but on-chip ECC schemes cannot be tested because parity bits are stored in separate regions preventing simultaneous write and read operations
Solution Approach 1:
The memory device is divided into normal cell regions and parity cell regions, with separate write and read operations performed on each region. The write circuit writes test data to normal cells while the read circuit reads parity bits from parity cells, enabling parallel operations that accommodate the ECC scheme's structural requirements while maintaining test efficiency
Solution Approach 2:
A temporary storage circuit is introduced as an intermediary component to store parity bits generated during the write operation. This temporary storage enables the separation of write and read operations in time, allowing the write circuit to complete its operation before the read circuit accesses the parity bits, thus resolving the conflict between parallel testing and ECC scheme requirements
2Reliability
If parity bits are stored in separate parity cell regions from normal cells, then error correction functionality is maintained, but parallel testing cannot be performed by writing and reading the same test data simultaneously across all memory cells
Solution Approach 1:
The testing process is segmented into separate write and read phases, with the write circuit operating on normal cell regions and the read circuit operating on parity cell regions. This segmentation maintains the functional separation required for error correction while enabling parallel testing operations that improve throughput compared to sequential testing
Solution Approach 2:
The write circuit performs preliminary writing of test data to normal cells before the read circuit reads parity bits from parity cells. This preliminary action ensures that the test data is already in place when parity bits are read, enabling efficient parallel testing without compromising the error correction capability that relies on the separation between normal and parity cells
Data Source
AI summary
A test method for a memory device which includes performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit, performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region, performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit, and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.