Memory ECC Circuit Testing with Isolated Parity Data Paths
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Solution Overview
Problem
Existing semiconductor memory devices with error correction functions face challenges in accurately testing error correction circuits due to interference from defective memory cells, leading to potential false determination of circuit defects.
Innovation Solution
A semiconductor memory device design that includes a parity generating circuit, normal and parity memory cell arrays, data latching sections, and an error correction circuit, allowing for independent testing of the error correction circuit and parity generating circuit, irrespective of the presence of defective memory cells, by using input and parity data for testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data is written to memory cells and read out for testing, then the error correction circuit can be tested, but defective memory cells may cause false determination of circuit defects
Solution Approach 1:
The patent extracts the testing process from the memory cell array by providing a dedicated test data input terminal and test result output terminal that bypass the memory cells. This allows the error correction circuit to be tested independently without interference from defective memory cells, resolving the contradiction between being able to test the circuit and avoiding false defect determination.
2Ease of operation
If memory cells are used for testing, then the testing process can be simplified, but defective memory cells interfere with accurate error correction circuit testing
Solution Approach 1:
The patent segments the testing function from the storage function by providing separate test data input and test result output paths that do not involve the memory cell array. This segmentation allows independent testing of the error correction circuit with the same operational simplicity as memory cell-based testing, but without the interference from defective cells.
3Productivity
If physically defective memory cells are used, then device yield is improved, but error correction testing becomes inaccurate
Solution Approach 1:
The patent extracts the error correction circuit testing from the memory cell array operation, allowing devices with defective memory cells to still be yielded while maintaining accurate error correction circuit testing through dedicated test terminals that bypass the problematic memory cells.
Data Source
AI summary
A semiconductor memory device includes: a parity generating circuit for generating parity data corresponding to input data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for selectively outputting the input data or the parity data; a parity data latching section for latching and outputting the output from the input selection circuit or data read out from the parity memory cell array; and an error correction circuit for performing an error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing an error correction if an error is detected, to output the obtained result. The parity data latching section outputs the data latched by itself externally of the semiconductor memory device.