Semiconductor Memory Devices With Dynamic ECC Path Selection
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Solution Overview
Problem
The increasing bit errors in DRAM memory cells due to shrinking fabrication design rules pose a challenge in maintaining the high speed and cost efficiency of semiconductor memory devices.
Innovation Solution
A semiconductor memory device is designed with a memory cell array, control logic circuit, error correction circuit, and path selection circuits that allow data to bypass or pass through the error correction circuit based on a density mode, using distinct sub-arrays for data and parity storage, optimizing storage capacity and error correction in different modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is always passed through the error correction circuit, then bit errors can be corrected, but storage capacity is reduced and operation speed decreases
Solution Approach 1:
The patent implements dynamic path selection by controlling multiplexers to switch between two data paths based on the density mode signal. In first density mode, data bypasses the error correction circuit for high-speed operation; in second density mode, data passes through the error correction circuit for enhanced reliability. This dynamic switching resolves the contradiction between speed and error correction.
Solution Approach 2:
The patent changes the operational parameter of the error correction circuit by introducing a density mode signal that controls whether ECC is applied. This parameter change allows the system to adapt between high-speed mode (ECC disabled) and high-reliability mode (ECC enabled), resolving the contradiction between operation speed and bit error correction capability.
2Reliability
If error correction circuit is used for all data, then reliability increases, but storage capacity decreases
Solution Approach 1:
The patent segments the memory system into two distinct operational modes: first density mode without ECC for maximum storage capacity, and second density mode with ECC for enhanced reliability. The density mode signal segments the data flow, directing it through different paths based on the required mode, thus resolving the contradiction between storage capacity and error correction capability.
Solution Approach 2:
The memory device is designed with multi-functionality to operate in two density modes. The same memory device can provide either maximum storage capacity (first density mode) or enhanced reliability with error correction (second density mode), making it universally adaptable to different application requirements and resolving the contradiction between storage capacity and reliability.
3Quantity of substance
If fabrication design rules are shrunk to increase density, then storage capacity increases, but bit errors increase
Solution Approach 1:
The patent implements a dynamic response to increased bit error rates from shrunk fabrication rules. The density mode signal dynamically enables or disables the error correction path based on observed error rates, allowing the system to maintain high storage density while compensating for increased bit errors through selective ECC application.
Solution Approach 2:
The patent converts the harmful effect of increased bit errors (resulting from fabrication rule shrinkage) into a beneficial feature by enabling the error correction circuit. The density mode signal activates ECC when bit errors increase, transforming the problem of higher error rates into an opportunity to demonstrate enhanced error correction capability, thus resolving the contradiction between storage density and reliability.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.