Memory Controller ECC Speed Control During Peak Current

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Solution Overview

Problem

Existing memory controllers face challenges in efficiently managing power consumption and error correction operations during peak current periods, leading to increased voltage drops and malfunction probabilities.

Innovation Solution

A memory controller with a power manager that monitors peak current periods and adjusts error correction operations by controlling speed and frequency based on peak sensing information, thereby reducing peak current magnitude and maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If error correction operations are performed at high speed continuously, then productivity is improved, but power consumption increases and voltage drops occur during peak current periods

Engineering Contradiction:
Improveerror correction operation speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the error correction operation speed variable rather than constant. The ECC engine dynamically adjusts its operating speed based on real-time power management signals from the PMIC, transitioning between high-speed mode (when power is sufficient) and low-speed mode (when power consumption needs reduction). This dynamic speed adjustment resolves the contradiction by allowing high productivity when energy is available while preventing excessive power consumption and voltage drops when energy resources are constrained.

Inventive Principle:
Principle #15Dynamics

2Productivity

If error correction operations are performed continuously at high speed, then productivity is improved, but reliability deteriorates due to voltage drops and malfunctions

Engineering Contradiction:
Improveerror correction operation speedVSAvoidoperation stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback control through the interaction between the PMIC and ECC engine. The PMIC monitors power consumption and voltage levels in real-time, then provides feedback signals to the ECC engine to adjust its operating speed accordingly. When voltage drops or power consumption exceeds thresholds, the PMIC signals the ECC engine to reduce speed, preventing malfunctions and maintaining system reliability. This closed-loop feedback mechanism resolves the contradiction by continuously adapting productivity to maintain stable operating conditions.

Inventive Principle:
Principle #23Feedback

3Use of energy by moving object

If error correction operations are slowed down to reduce peak current, then power consumption is reduced, but productivity decreases

Engineering Contradiction:
Improvepower consumptionVSAvoiderror correction operation speed
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent applies periodic action by alternating between high-speed error correction operations and low-speed operations in response to periodic power management requirements. Rather than maintaining a constantly reduced speed, the system operates at high speed during periods when power consumption can be sustained, then reduces speed during peak current periods to manage power consumption. This periodic modulation of operation speed allows the system to achieve both reduced power consumption during critical periods and maintained productivity during acceptable periods.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250363000A1Memory controller and operating method thereof
Publication Date: 2025.11.27 SK HYNIX INC
  • US20250363000A1 patent drawing
  • US20250363000A1 patent drawing
  • US20250363000A1 patent drawing

AI summary

A memory controller for efficiently managing power may include a memory interface, a power manager, and an Error Correction Code (ECC) engine. The memory interface may perform a data input/output operation of transmitting/receiving data to/from a memory device through an input/output line. The power manager may monitor a peak current period of the data input/output operation, and generate peak sensing information when the peak current period is sensed. The ECC engine may perform an error correction operation on the data while the data input/output operation is performed, and control a speed of the error correction operation in the peak current period in response to the peak sensing information.