Memory ECC Switching for Persistent Read Error Correction

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Solution Overview

Problem

Current error correction methods in memory systems are inadequate in handling errors that persist after normal read operations and retry operations, as they often rely on general Reed-Solomon algorithms without effective mechanisms for erasure correction.

Innovation Solution

The proposed method involves a dual operation mode in memory systems, where a first mode uses general Reed-Solomon decoding and a second mode employs an erasure-loop method with a loop-buffer and loop-counter to iteratively correct errors by sequentially erasing symbols, enhancing error correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If general Reed-Solomon decoding is used in normal read operations, then the ease of operation is maintained, but the reliability is insufficient for persistent errors

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error correction process is segmented into two distinct operation modes: a first mode using general Reed-Solomon decoding for normal operations, and a second mode using erasure-loop method for persistent errors. This segmentation allows each mode to be optimized for its specific purpose without requiring the full complexity of both approaches simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between two operation modes based on error correction needs. The controller determines when to transition from the first operation mode (general Reed-Solomon) to the second operation mode (erasure-loop method), allowing the system to adapt its complexity level according to the actual error conditions encountered.

Inventive Principle:
Principle #15Dynamics

2Reliability

If iterative erasure correction is implemented for persistent errors, then the reliability improves, but the loss of time increases due to multiple decoding operations

Engineering Contradiction:
Improvepersistent error correctionVSAvoiddecoding operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary error correction using the first operation mode (general Reed-Solomon decoding) before attempting the more time-consuming second operation mode (erasure-loop method). This preliminary action removes many errors early, so that the iterative erasure correction only needs to handle remaining persistent errors, reducing the total time loss.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system skips the iterative erasure correction process for errors that can be corrected by the faster first operation mode. By rushing through the quick correction path when sufficient, the system avoids the time penalty of multiple decoding operations unless absolutely necessary.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Adaptability or versatility

If a dual operation mode system is implemented, then the adaptability to different error conditions improves, but the device complexity increases

Engineering Contradiction:
Improveerror handling flexibilityVSAvoidoperation mode management
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The controller is designed with multi-functionality, capable of managing both the first operation mode (general Reed-Solomon decoding) and the second operation mode (erasure-loop method). This universal controller handles mode selection, switching, and coordination, allowing the system to adapt to different error conditions without requiring separate dedicated hardware for each mode.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the two different decoding approaches (general Reed-Solomon and erasure-loop method) into a unified error correction system managed by a single controller. By combining these functions under one management structure, the system achieves adaptability to various error conditions while minimizing the complexity increase that would result from completely separate implementations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11392457B2Error correction method of a memory system
Publication Date: 2022.07.19 SK HYNIX INC
  • US11392457B2 patent drawing
  • US11392457B2 patent drawing
  • US11392457B2 patent drawing

AI summary

An error correction method includes performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer in a second operation mode.