Memory ECC Puncturing for Heterogeneous CXL Reliability
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Solution Overview
Problem
Existing memory systems in Compute Express Link (CXL) environments face inefficiencies due to the application of high-reliability error correction codes (ECC) to both volatile and non-volatile memories, leading to unnecessary resource wastage and performance overhead.
Innovation Solution
The implementation of a memory device that applies differential Error Correction Code (ECC) with puncturing options, allowing for reduced redundancy and customized ECC configurations based on the reliability characteristics of different memory types, thereby optimizing error correction for heterogeneous memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-reliability error correction codes (ECC) are applied to both volatile and non-volatile memories, then error correction capability is improved, but resource wastage and performance overhead increase
Solution Approach 1:
The patent applies differential ECC strategies where volatile memory devices receive punctured ECC with reduced redundancy while non-volatile memory devices receive original ECC with full redundancy. This local differentiation matches the reliability characteristics of each memory type, providing adequate error correction for non-volatile memory while reducing unnecessary computational overhead for volatile memory.
Solution Approach 2:
The patent changes the ECC parameter (redundancy level) based on the memory device type. By using puncturing options, the system dynamically adjusts the ECC code length and redundancy for different memory devices, optimizing the balance between error correction capability and computational resource consumption.
2Reliability
If high-reliability error correction codes (ECC) are applied to both volatile and non-volatile memories, then error correction capability is improved, but system performance deteriorates due to performance overhead
Solution Approach 1:
The patent implements local quality by applying different ECC schemes to different memory types. Volatile memory devices use punctured ECC with lower redundancy, while non-volatile memory devices use original ECC with full redundancy. This differentiated approach improves system performance by reducing the computational burden on volatile memory operations while maintaining robust error correction for non-volatile memory.
Solution Approach 2:
The patent applies partial ECC action to volatile memory through puncturing, where only a portion of the full ECC redundancy is applied. This partial action is sufficient for volatile memory's inherent reliability characteristics, avoiding the excessive computational overhead of applying full-strength ECC to all memory devices.
3Reliability
If high-reliability error correction codes (ECC) are applied to both volatile and non-volatile memories, then error correction capability is improved, but resource usage increases unnecessarily
Solution Approach 1:
The patent applies local quality by providing different levels of ECC redundancy to different memory devices based on their reliability characteristics. Non-volatile memory devices receive full ECC redundancy, while volatile memory devices receive reduced redundancy through puncturing. This eliminates unnecessary resource consumption while maintaining adequate error correction capabilities.
Solution Approach 2:
The patent extracts unnecessary redundancy from the ECC codes applied to volatile memory devices through the puncturing process. By removing redundant check bits that are not needed for volatile memory's error correction requirements, the system reduces resource usage while maintaining sufficient reliability.
Data Source
AI summary
A memory device includes a first memory device configured to store a first error correction code of a first size during a first write operation, a second memory device configured to store a second error correction code of a second size, larger than the first size, during a second write operation, and a control logic circuit configured to control the first memory device and the second memory device. The control logic circuit includes an error correction circuit configured to generate one of the first error correction code and the second error correction code for write data according to puncturing option information.