Memory ECC Architecture for Selective Read Error Correction
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Solution Overview
Problem
As memory device density increases, it becomes increasingly difficult to fabricate devices with no failed memory cells, leading to the need for error correction mechanisms to address errors in read and write processes.
Innovation Solution
Incorporating an error correction code generation circuit and an in-memory error correction circuit within the memory system to generate and utilize error correction codes for data storage and retrieval, correcting errors of up to N bits during read operations while maintaining the integrity of data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory device density is increased to improve storage capacity, then productivity and storage capacity are improved, but manufacturing precision and reliability deteriorate due to increased difficulty in fabricating devices with no failed memory cells
Solution Approach 1:
The patent divides the memory device into functional segments: original memory cells for data storage and separate redundant memory cells for error correction. This segmentation allows the system to tolerate failures in original cells while maintaining overall reliability, resolving the contradiction between high density and manufacturing precision.
Solution Approach 2:
The patent performs preliminary error correction by generating ECC codes during the write operation and storing them alongside the data. This preliminary action prepares the system to correct errors before read operations, addressing the reliability issue that arises from increased density.
2Reliability
If error correction circuits are added to correct errors in read and write processes, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error correction functionality with the existing memory structure by integrating ECC generation and correction circuits into the memory device architecture. This combining approach provides comprehensive error correction while avoiding the need for entirely separate correction systems, thus managing device complexity.
Solution Approach 2:
The memory device performs self-correction of errors using its own integrated ECC circuits. The device generates ECC codes during writing and automatically corrects errors during reading without requiring external intervention, improving reliability while keeping the system architecture relatively simple.
3Loss of time
If in-memory error correction is performed to improve error correction efficiency, then error correction speed is improved, but reliability may deteriorate due to potential malfunction of in-memory correction circuits
Solution Approach 1:
The patent implements a hybrid error correction approach where the in-memory correction circuit attempts to correct errors up to a certain threshold (partial action), and if that fails or is not performed, the host system performs additional correction (excessive action). This layered approach ensures that time-sensitive corrections are handled quickly in-memory while more reliable host-level correction provides a safety net.
Data Source
AI summary
A memory system includes an error correction code (“ECC”) generation circuit using write data to generate an ECC to be stored together with the write data; a memory device, during a write operation, storing received data and a received ECC in a memory core, and, during a read operation, checking for an error in data read from the memory core, correcting the error in read data using the ECC and outputting error-corrected data and the ECC, when the error in the read data is between one bit and N bits inclusive, and outputting the read data and the ECC when no error is present in the read data or the error in the read data exceeds N bits; and an error correction circuit correcting, when an error is present in data outputted from the memory device, the error in the data outputted using an ECC outputted from the memory device.