Memory Controller ECC Pipelining for Remote Read Latency

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Solution Overview

Problem

Remote memory devices in memory systems, such as nonvolatile memory, introduce higher latency due to error correction code (ECC) algorithms, which negatively impact system performance.

Innovation Solution

Pipelining ECC correction logic with data transfer to the host, allowing remote memory devices to return data before ECC completion, and storing it in local memory until ECC indicators confirm data integrity or require correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC algorithms are implemented in remote memory devices, then data integrity is improved, but read operation latency increases

Engineering Contradiction:

Improvedata integrityVSAvoidread operation latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing ECC processing in parallel with data transfer. The memory controller initiates ECC processing on the data immediately after receiving it from the remote memory device, while simultaneously receiving additional data or preparing for the next operation. This overlapping of operations allows the system to prepare error correction before it is strictly needed, reducing the critical path latency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by maintaining parallel processing streams. While ECC processing is being performed on one data set, the memory controller continues to receive data, issue commands, or process other tasks. This eliminates idle waiting time and keeps the system continuously productive, effectively hiding the ECC processing latency from the critical path.

Inventive Principle:

Principle #20Continuity of useful action

2Loss of time

If data is returned to host before ECC completion, then latency is reduced, but data reliability risk increases

Engineering Contradiction:

ImprovelatencyVSAvoiddata reliability

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent employs feedback mechanisms where the memory controller continuously monitors the status of ECC processing and data transfer operations. Based on this feedback, the controller dynamically determines when data can be safely returned to the host. The feedback loop ensures that data integrity checks are completed or appropriately handled before data is made available to the host, maintaining reliability while optimizing latency.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The memory controller acts as an intermediary between the remote memory device and the host. It receives data from the remote memory device, manages the ECC processing pipeline, and only returns data to the host when appropriate. This intermediary role allows the system to decouple the data transfer timing from the ECC completion timing, enabling latency optimization without compromising data reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10572339B2Memory latency management

Publication Date: 2020.02.25 SK HYNIX NAND PRODUCT SOLUTIONS CORP

AI summary

Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.