Memory Control Circuit Layout for Distributed ECC Reading

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Solution Overview

Problem

Existing rewritable non-volatile memory modules face inefficiencies in data reading due to uneven distribution of error correcting codes, leading to suboptimal memory usage and reading performance.

Innovation Solution

A data writing method that evenly distributes array error correcting codes across different chip enable groups and planes within the memory module, using distinct programming modes and sequences to correct data stored in physical programming units, thereby improving data reading efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correcting codes are stored in separate memory chips, then data security is improved, but memory usage efficiency deteriorates and data reading efficiency deteriorates

Engineering Contradiction:
Improvedata securityVSAvoiddata reading efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides error correcting codes into multiple segments (first array error correcting code and second array error correcting code) and distributes them across different chip enable groups. This segmentation allows the system to maintain data security through distributed storage while improving reading efficiency by enabling parallel access to code segments from multiple chip enables simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines the storage of error correcting codes with the storage structure of data itself by integrating codes into the same memory architecture rather than using separate dedicated storage. This merging allows the memory system to utilize existing read/write pathways for both data and codes, improving overall efficiency while maintaining security through distributed placement across multiple chip enables.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If error correcting codes are stored in separate memory chips, then data security is improved, but memory space utilization deteriorates

Engineering Contradiction:
Improvedata securityVSAvoidmemory space utilization
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent makes the memory architecture universal by using the same memory structure for both data storage and error correcting code storage. The chip enable groups serve dual purposes: storing user data and storing distributed error correcting codes. This multi-functionality eliminates the need for separate dedicated code storage space, improving overall memory utilization while maintaining security through distributed placement.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If all data is stored in a single plane, then programming is simplified, but reading efficiency deteriorates due to uneven distribution of error correcting codes

Engineering Contradiction:
Improveprogramming simplicityVSAvoidreading efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent applies local quality by distributing error correcting codes to specific locations across different chip enable groups rather than concentrating them in one location. Each chip enable group contains a portion of the codes appropriate for correcting data in its associated planes, creating locally optimized error correction capability that improves overall reading efficiency while maintaining manageable programming through systematic distribution patterns.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent transitions from a single-plane storage architecture to a multi-dimensional architecture that distributes data and codes across multiple chip enable groups and planes. This dimensional expansion allows the system to maintain programming simplicity through structured distribution while dramatically improving reading efficiency by enabling parallel access to data and its corresponding error correcting codes from multiple planes simultaneously.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11101822B1Data writing method, memory control circuit unit and memory storage apparatus
Publication Date: 2021.08.24 PHISON ELECTRONICS
  • US11101822B1 patent drawing
  • US11101822B1 patent drawing
  • US11101822B1 patent drawing

AI summary

A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving first data and second data from a host system; generating a first array error correcting code based on the first data, and generating a second array error correcting code based on the second data; programming a first group including the first array error correcting code into a first chip enable group by using a first programming mode; and programming a second group including the second array error correcting code into a second chip enable group by using a second programming mode.