Memory ECC Check Vectors Using Reducible GF(2) Polynomials
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error detection and correction techniques in computer memories, such as those using irreducible polynomials, face limitations in guaranteeing a minimum Hamming distance, making them less effective for detecting and correcting errors in memory components.
Innovation Solution
A memory system employing reducible polynomials with GF(2) coefficients for error detection and correction, organized into arrays with row and inner check bits, allows for single-bit correction within a single memory component and multi-bit detection across components, ensuring robust error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an irreducible GF(2) polynomial is used for error detection and correction, then the code structure is well-defined, but the possible polynomials are significantly limited making it harder to guarantee a minimum Hamming distance
Solution Approach 1:
The patent changes the fundamental parameter of polynomial irreducibility to reducibility. By using reducible GF(2) polynomials instead of irreducible ones, the system expands the available polynomial choices while maintaining the ability to guarantee minimum Hamming distance through careful selection of check vectors from the residue system.
Solution Approach 2:
The patent segments the polynomial structure by using a reducible polynomial that can be factored into irreducible components. This segmentation allows the check vectors to be constructed from the residue system modulo the reducible polynomial, providing both flexibility in polynomial choice and guarantees on Hamming distance through the structured factorization.
2Reliability
If more check bits are added to increase error detection capability, then error detection reliability improves, but device complexity increases
Solution Approach 1:
The patent makes the check vectors universal by selecting them from the residue system modulo a reducible polynomial. This universal selection method allows the same mathematical framework to handle both single-bit and multi-bit errors, as well as component failures, without requiring separate complex check structures for each error type.
Solution Approach 2:
The patent changes the parameter of polynomial reducibility to enable more efficient check vector construction. By working with reducible polynomials and their residue systems, the system can generate check vectors that provide comprehensive error detection and correction capabilities with optimized check bit requirements compared to traditional irreducible polynomial approaches.
Data Source
AI summary
A memory system is described that provides error detection and correction after a failure of a memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-2 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and an inner check bit column including X inner check bits. The inner check bits are defined to cover bits in the array according to a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system. Moreover, each column is stored in a different memory component, and the check bits are generated from the data bits to provide block-level detection and correction for both memory errors and a failed memory component.