Memory Device ECC and Redundancy Repair Control Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advancements in semiconductor manufacturing have led to increased memory capacity, but this has resulted in a higher number of defective memory cells, reducing manufacturing yield and memory capacity reliability, necessitating methods to repair 'fail' cells effectively.
Innovation Solution
A memory device that performs both error correction code (ECC) operations and redundancy repair operations, utilizing a control logic circuit to selectively apply ECC or redundancy repair based on the type of 'fail' cells, with separate memory cell blocks for ECC and redundancy operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor manufacturing technology is advanced to increase memory capacity, then memory capacity increases, but the number of defective memory cells increases
Solution Approach 1:
The memory device is divided into first memory cell blocks for normal data storage and a second memory cell block for redundancy repair. This segmentation allows defective cells in the first blocks to be repaired by replacing them with corresponding cells from the second block, thereby maintaining high memory capacity while compensating for the increased defective cell rate through structured redundancy allocation.
2Reliability
If only ECC operation is used for repairing fail cells, then single-bit errors can be corrected, but multi-bit errors cannot be repaired
Solution Approach 1:
The second memory cell block serves multiple functions: it provides redundancy repair for both single-bit and multi-bit errors, and also serves as ECC storage. The control logic circuit determines whether to perform redundancy repair or ECC operation based on the type of error detected, making the system universally capable of handling different error types through a single unified structure.
3Adaptability or versatility
If redundancy repair operation is always used, then all types of fail cells can be repaired, but the fail repair rate decreases due to excessive redundancy allocation
Solution Approach 1:
The system dynamically selects between redundancy repair and ECC operations based on the type of error detected. The control logic circuit compares the address of the fail cell with the applied address to determine whether to perform redundancy repair or ECC operation, allowing the system to adaptively optimize the repair approach for each specific error case rather than always using redundancy repair.
4Reliability
If separate memory cell blocks are used for ECC and redundancy operations, then both operations can be performed effectively, but device complexity increases
Solution Approach 1:
The second memory cell block combines both redundancy repair and ECC functions in a single unified structure. Instead of having completely separate blocks for redundancy and ECC, the patent merges these functions into one block that serves both purposes, reducing overall device complexity while maintaining the effectiveness of both repair operations through shared hardware resources.
Data Source
AI summary
Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.