Memory Array ECC Interleaving for Refresh and Speed Tradeoffs
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Solution Overview
Problem
Existing memory devices face performance penalties due to the need for frequent refresh operations to prevent data corruption from leakage in DRAM, which consumes power and interrupts read/write operations, and existing error correction schemes compromise operational speed and circuit real estate.
Innovation Solution
The solution involves dividing the column cycle into two halves to allow for error correction and check bit regeneration during an interleaved column cycle, enabling extended refresh times and reducing the frequency of refresh operations, while maintaining fast clock rates for data operations by interleaving read/modify/write processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent data corruption from leakage in DRAM, then data reliability is improved, but power consumption increases and read/write operations are interrupted
Solution Approach 1:
The patent applies preliminary action by performing error correction code generation and check bit regeneration during the refresh interval before data corruption occurs. The system proactively corrects potential errors during the refresh period, allowing extended refresh times and reducing the frequency of refresh operations needed, thereby reducing power consumption while maintaining data reliability
Solution Approach 2:
The patent implements continuity of useful action by interleaving read/modify/write processes with error correction operations. The column cycle is divided into two halves, allowing error correction to occur during the refresh interval without interrupting the continuous stream of data operations, maintaining both reliability and operational efficiency
2Reliability
If error correction schemes are implemented to enhance memory array data storage reliability, then data reliability is improved, but operational speed and circuit real estate are compromised
Solution Approach 1:
The patent applies segmentation by dividing the column cycle into two distinct halves: the first half dedicated to read operations and the second half to write operations with error correction. This segmentation allows error correction code generation and check bit regeneration to occur during the refresh interval without slowing down the overall operational speed of the memory device
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that error correction operations occur during the refresh interval, which would otherwise be idle time. The interleaved read/modify/write processes continue without interruption, maintaining operational speed while improving data storage reliability through error correction
Data Source
AI summary
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.