Semiconductor Memory ECC Switching for Data Retention Errors
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices with laminated gate structures face issues with data retention over time, leading to errors and the wasteful use of high-performance error correction mechanisms, which consume power and have large circuit scales, even for short data storage times.
Innovation Solution
A semiconductor memory device with error correction circuits that generate detecting codes and correcting codes to detect and correct errors, using a combination of low-power Hamming codes for initial error correction and high-capability codes like Reed-Solomon codes for longer retention times, optimizing circuit scale and power consumption based on error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-performance error correction mechanism is used to guarantee correct information restoration after long storage, then error correction capability is improved, but power consumption and circuit scale increase
Solution Approach 1:
The patent applies dynamics by making the error correction mechanism adaptive rather than static. The control circuit dynamically selects between first and second error correction mechanisms based on the actual elapsed time from information storage, transitioning from a fixed high-performance mechanism to a variable selection system that optimizes performance based on real-time conditions.
Solution Approach 2:
The patent changes the parameter of error correction capability based on elapsed time. By using the elapsed time detection circuit to determine whether to apply the first or second error correction mechanism, the system adjusts the error correction capability parameter dynamically, using stronger correction only when necessary for long-stored data.
2Reliability
If a high-performance error correction mechanism is used for all data regardless of storage time, then error correction capability is improved, but processing time increases
Solution Approach 1:
The system dynamically adjusts processing intensity based on storage time. For recently stored data, the simpler first error correction mechanism is used, reducing processing time. For long-stored data, the more capable second mechanism is activated, ensuring reliability without unnecessarily extending processing time for all operations.
Solution Approach 2:
The patent applies partial action by using the sufficient (not excessive) error correction mechanism appropriate for each case. For short-storage-time data, the first mechanism provides adequate correction without the overhead of the second mechanism, avoiding unnecessary processing time while maintaining sufficient error correction capability.
3Reliability
If error correction is performed on concatenated data blocks, then error correction capability is improved, but data access efficiency decreases
Solution Approach 1:
The patent segments the error correction process into two levels: first error correction mechanisms applied to individual data blocks, and a second error correction mechanism applied to concatenated blocks when needed. This segmentation allows efficient processing of small data units while providing optional enhanced correction for larger concatenated structures, balancing capability with access efficiency.
Solution Approach 2:
Different error correction qualities are applied locally based on data characteristics. The first error correction mechanism provides baseline protection for all data blocks, while the second mechanism provides enhanced protection specifically for concatenated blocks that require it, creating local quality variations that optimize both efficiency and reliability.
Data Source
AI summary
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.