Semiconductor Memory ECC Switching for Data Retention Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile semiconductor memory devices with laminated gate structures face issues with data retention over time, leading to errors, and current high-performance error correction mechanisms are wasteful in power consumption and circuit size, as they are applied uniformly regardless of storage time, even for short-term data.
Innovation Solution
A semiconductor memory device with multiple error correction code generators: first correcting codes for low power and small circuits to handle short-term errors, and a second correcting code for high-capability error correction, allowing adaptive error correction based on elapsed time, reducing unnecessary power usage and circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-performance error correction mechanism is applied uniformly regardless of storage time, then error correction capability is improved, but power consumption and circuit scale increase unnecessarily
Solution Approach 1:
The patent implements dynamic error correction by switching between different correction mechanisms based on the elapsed time since data storage. A first error correction mechanism with lower power consumption is used for short-term data, while a second error correction mechanism with higher correction capability is activated for long-term data. This dynamic adaptation resolves the contradiction by making the system's error correction capability variable rather than fixed, thereby reducing unnecessary power consumption while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of error correction capability based on the time parameter. By monitoring the elapsed time since data storage and adjusting the error correction mechanism accordingly, the system optimizes the balance between reliability and power consumption. This parameter-based control allows the system to use minimal power for short-term storage while providing enhanced correction for long-term storage needs.
2Reliability
If a high-performance error correction mechanism is applied uniformly, then error correction capability is improved, but circuit scale increases
Solution Approach 1:
The patent segments the error correction function into two distinct mechanisms: a first error correction mechanism for short-term data with simpler circuitry, and a second error correction mechanism for long-term data with more complex but higher-capability circuits. This segmentation allows the system to deploy only the necessary correction capability for each data type, thereby reducing the overall circuit scale compared to implementing a single high-performance correction mechanism for all data.
Solution Approach 2:
The system dynamically selects between different error correction circuits based on storage time, avoiding the need to permanently instantiate a large high-performance correction circuit for all data paths. This dynamic approach reduces the average circuit scale while maintaining the ability to provide high error correction capability when needed.
3Reliability
If error correction capability is increased by reading larger data blocks, then error correction capability is improved, but power consumption increases due to reading more data
Solution Approach 1:
The patent implements dynamic data block selection based on storage time. For short-term data, the system reads smaller data blocks that require less power, while for long-term data, it reads larger data blocks to utilize the higher error correction capability of the second mechanism. This dynamic block size adaptation resolves the contradiction by matching the read operation scale to the actual error correction needs, thereby reducing unnecessary power consumption from reading excessive data.
Data Source
AI summary
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.