Memory ECC Decoder Selection for Row Hammer Error Correction
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Solution Overview
Problem
The row hammering phenomenon in memory cells, where data loss occurs due to high activation counts, is addressed by performing target refresh operations on adjacent rows, but existing error correction methods are inefficient and complex.
Innovation Solution
Implementing a first and second ECC decoder circuit to correct errors in memory cells using parity, with a selection circuit to choose the best correction result, and a counting circuit to update error correction data, allowing for efficient correction of 1-bit random and 2-bit adjacency errors using reduced parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ECC decoder circuits are used to correct errors in counting data, then data correction capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the counting data into multiple segments (first counting data, second counting data, third counting data) and applies separate ECC decoder circuits to each segment. This segmentation allows parallel error correction processing, improving reliability while managing complexity through modular design. Each decoder circuit handles a specific portion of the data, making the overall system more manageable.
Solution Approach 2:
The patent merges the outputs of multiple ECC decoder circuits through a selection circuit that chooses the most reliable correction result. By combining the correction capabilities of multiple decoders and selecting the best outcome, the system achieves enhanced data correction capability without proportionally increasing overall system complexity.
2Reliability
If target refresh operation is performed on adjacent rows to prevent row hammering, then reliability is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary error correction on counting data before using it to determine target refresh operations. By correcting errors in advance, the system ensures accurate identification of rows needing refresh without delaying the refresh process itself, thus maintaining reliability while minimizing time loss.
Solution Approach 2:
The ECC correction system operates autonomously on counting data to identify and correct errors that would otherwise require manual intervention or extended refresh operations. This self-correcting mechanism reduces the burden on the refresh operation timeline while maintaining data integrity.
3Productivity
If counting data is stored in adjacent memory cells, then access efficiency is improved, but susceptibility to row hammering increases
Solution Approach 1:
The patent converts the vulnerability of adjacent memory cell storage by applying error correction codes that specifically address row hammering-induced errors. The ECC system transforms the potential harm from adjacent cell proximity into a manageable condition through systematic error detection and correction, allowing efficient access while protecting against row hammering effects.
Solution Approach 2:
The ECC decoder circuits act as intermediaries between the adjacent memory cells and the processing logic. They mediate the data flow, correcting errors introduced by row hammering before the data affects system operations, thus enabling efficient access to adjacent cells while protecting against their vulnerability.
Data Source
AI summary
A memory including a first ECC decoder circuit configured to correct errors of first data having multiple bits and second data having one or more bits by using the first data, the second data, and a first parity and generate first error correction results, a second ECC decoder circuit configured to correct errors of the first data and third data having one or more bits by using the first data, the third data, and the first parity and generate second error correction results, and a first selection circuit configured to select one of the first error correction results and the second error correction results.