Memory ECC Scrubbing With Long Code Words for Data Retention
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Solution Overview
Problem
Non-volatile memory technologies like MRAM face challenges with read and write performance due to read-disturb errors and hard breakdown at high voltage operations, requiring advanced error correction methods to ensure long-term data retention, especially at higher temperatures, while also being sensitive to environmental disturbances and power consumption.
Innovation Solution
The implementation of an error correcting memory system that includes a data scrubbing circuit electrically coupled to both data and ECC memories, capable of correcting errors using a longer code word length than normal access, and featuring an environmental disturbance sensor to generate scrub data commands based on detected conditions, such as temperature and magnetic fields, to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If advanced error correction methods are used to ensure long-term data retention at higher temperatures, then data reliability is improved, but device complexity increases
Solution Approach 1:
The memory system is divided into multiple memory banks, each independently protected by its own error correction code. This segmentation allows error correction to be applied locally to each bank rather than requiring a complex system-wide correction mechanism, reducing overall device complexity while maintaining reliability.
Solution Approach 2:
Error correction codes are generated and stored in advance alongside the data in the memory banks. This preliminary action allows errors to be corrected during read operations without requiring complex real-time computation, simplifying the error correction circuitry needed during actual data access.
2Reliability
If two-bit correcting circuit is used to achieve long-term data retention, then data reliability is improved, but read and write operation speed decreases
Solution Approach 1:
By dividing the memory into multiple smaller banks, each with its own error correction code, the system can correct errors in parallel across banks during read operations. This segmentation reduces the time required for error correction compared to a single large two-bit correcting circuit, improving operation speed while maintaining reliability.
Solution Approach 2:
The system uses single-bit error correction codes for each memory bank rather than comprehensive two-bit correction. This partial action approach corrects the most common error type (single-bit errors) efficiently, achieving sufficient reliability without the excessive complexity and speed penalty of full two-bit correction.
3Area of stationary object
If larger blocks of data are protected with less ECC check bits using BCH code or LDPC code, then area overhead is reduced, but encoding and decoding complexity increases
Solution Approach 1:
The memory system segments data into multiple smaller banks, each protected by simple error correction codes. This segmentation allows the use of lightweight ECC schemes for each bank rather than requiring complex BCH or LDPC codes for large blocks, reducing encoding and decoding complexity while maintaining acceptable area overhead through the distributed structure.
Solution Approach 2:
Instead of implementing full-strength BCH or LDPC codes that would require complex encoding and decoding operations, the system uses simpler error correction codes for each memory bank. This partial protection approach reduces the complexity of encoding and decoding operations while still providing adequate error correction for the specific error rates expected in the application.
Data Source
AI summary
Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.