Memory Block ECC Scrubbing With Parallel Functional Transactions
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing error-related transactions across multiple memory blocks, particularly in ensuring accurate error detection and correction while maintaining performance.
Innovation Solution
The proposed solution involves a device and method that utilize control logic to manage error-related transactions on multiple memory blocks. This control logic enables concurrent execution of error correcting code (ECC) scrubbing transactions and functional transactions, allowing for efficient error detection and correction while minimizing performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-related transactions are performed sequentially on memory blocks, then error detection and correction accuracy is improved, but system productivity deteriorates due to transaction delays
Solution Approach 1:
The memory system is divided into multiple independent memory blocks (first memory block, second memory block, etc.), each capable of handling transactions independently. The control logic segments the error correction process by allowing different transactions to occur simultaneously on different blocks, thus maintaining reliability while improving throughput.
Solution Approach 2:
The control logic enables continuous operation by overlapping error-related transactions with non-error transactions across different memory blocks. While a first error-related transaction occurs on the first memory block, a non-error transaction can simultaneously occur on the second memory block, ensuring continuous useful action without interruption.
2Reliability
If error correcting code scrubbing transactions are executed on all memory blocks, then reliability is improved through comprehensive error correction, but device complexity increases due to coordinated transaction management
Solution Approach 1:
The control logic dynamically manages transactions based on real-time conditions of each memory block. Instead of rigidly executing the same transaction sequence on all blocks, the system adapts by allowing overlapping transactions, skipping error-related transactions on blocks that don't need them, and adjusting timing based on transaction status, thereby reducing coordination complexity while maintaining correction completeness.
Solution Approach 2:
Different memory blocks receive different treatment based on their specific needs. The control logic applies error correction transactions selectively - performing them on blocks that require correction while allowing non-error transactions to proceed on blocks that don't need correction. This localized approach reduces overall system complexity by avoiding unnecessary coordinated actions across all blocks.
3Productivity
If multiple error-related transactions are executed concurrently on different memory blocks, then productivity is improved through parallel processing, but measurement precision deteriorates due to timing synchronization challenges
Solution Approach 1:
The timing management is segmented by memory block, with each block having independent timing control for its transactions. The control logic tracks and manages timing separately for the first memory block, second memory block, and other blocks, allowing parallel execution while maintaining precise timing measurement for each segment independently, thus avoiding synchronization interference.
Data Source
AI summary
A device includes memory blocks; connections respectively coupled to the memory blocks; and control logic coupled to the memory blocks. The control logic is operable to control performance of error-related transactions on the memory blocks via the connections. Such control may include causing a first error-related transaction to be performed on a first memory block of the memory blocks during a first time period, causing a second error-related transaction to be performed on a second memory block of the memory blocks during a second time period, and causing a transaction that is not an error-related transaction to be performed on at least one of the memory blocks, except the first memory block, during performance of one or both of the first error-related transaction and the second error-related transaction.