Memory ECC Scrubbing With Long Code Words for Data Retention
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Solution Overview
Problem
Non-volatile memory technologies like MRAM face challenges in read and write performance due to read-disturb errors and hard breakdown at high voltage operations, requiring advanced error correction methods to ensure long-term data retention, especially at higher temperatures, while also being sensitive to environmental disturbances and power consumption.
Innovation Solution
The implementation of an error correcting memory system that includes a data scrubbing circuit electrically coupled to both data and ECC memories, capable of correcting errors using a longer code word length than normal access, and featuring an environmental disturbance sensor to generate scrub data commands based on detected conditions, such as temperature and magnetic fields, to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If advanced error correction methods are used to ensure long-term data retention at higher temperatures, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements data scrubbing that proactively detects and corrects errors before they accumulate to critical levels. The scrubbing circuit periodically reads data, detects errors using ECC, and corrects them in-place, preventing reliability degradation over time without requiring complex continuous correction mechanisms
Solution Approach 2:
The memory system is divided into data storage circuits and separate error correction circuits. The scrubbing function is implemented as a distinct modular component that operates independently, allowing the error correction functionality to be added without fundamentally redesigning the core memory architecture
2Reliability
If data scrubbing is performed to correct errors, then data reliability is improved, but read and write speeds may be affected
Solution Approach 1:
The scrubbing circuit operates periodically rather than continuously, performing error detection and correction at scheduled intervals. This periodic operation allows normal read and write operations to proceed at full speed between scrubbing cycles, minimizing impact on productivity while maintaining data integrity
Solution Approach 2:
The scrubbing circuit includes a buffer that mediates between the data storage circuit and the correction logic. During scrubbing operations, data is transferred to the buffer where correction occurs, allowing normal memory operations to continue accessing the buffer without being blocked by the correction process
3Reliability
If longer code word length is used for error correction, then error correction efficiency is improved, but memory area overhead increases
Solution Approach 1:
The scrubbing circuit performs error correction on a selective basis rather than continuously correcting all data. It monitors error rates and intensifies scrubbing activity when errors are detected, applying correction effort proportionally to the actual error conditions rather than uniformly across all memory operations
4Loss of energy
If power consumption is reduced, then energy efficiency is improved, but error rate for data retention and operations increases
Solution Approach 1:
The scrubbing circuit incorporates error rate monitoring that provides feedback to control the scrubbing intensity and frequency. When error rates are low, scrubbing activity is reduced to minimize power consumption. When error rates increase, the circuit automatically increases scrubbing frequency, creating a feedback-controlled balance between power efficiency and error correction effectiveness
Data Source
AI summary
Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.