Memory ECC Layout With Secondary Correction for High Bit Error Rates
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Solution Overview
Problem
Existing memory modules face challenges in maintaining data reliability due to high bit error rates, as current error correction codes (ECC) may not be sufficient to correct all errors, especially in lower quality memory dies, impacting performance and capacity.
Innovation Solution
Implementing a dual ECC system where primary ECC is supplemented by secondary ECC, spread across multiple memory dies, allowing for correction of more bit errors by accessing additional ECC data when primary ECC fails, without significantly impacting read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single ECC is used, then device complexity is low, but reliability is insufficient for high bit error rates
Solution Approach 1:
The ECC system is segmented into two distinct layers: primary ECC and secondary ECC. Each layer handles different error correction needs, with primary ECC providing baseline protection and secondary ECC providing enhanced protection for uncorrectable errors. This segmentation allows the system to achieve higher reliability without requiring a completely complex new ECC architecture.
Solution Approach 2:
The patent adds a temporal dimension to error correction by implementing a two-stage correction process. Instead of a single ECC layer, the system first attempts primary ECC correction, then falls back to secondary ECC for remaining errors. This dimensional approach to error correction enables handling of higher bit error rates while maintaining manageable system complexity through hierarchical organization.
2Reliability
If secondary ECC is added to correct more errors, then reliability improves, but read performance may be impacted
Solution Approach 1:
The system implements partial action by applying secondary ECC only when primary ECC fails to correct errors. This selective approach means that for the majority of cases where primary ECC succeeds, the system maintains fast read performance. Secondary ECC is activated only for the subset of cases requiring additional correction, thus improving reliability without significantly impacting overall read performance.
Solution Approach 2:
The patent performs preliminary error correction using primary ECC before attempting more complex secondary ECC correction. This preliminary action filters out most error cases that can be quickly corrected, allowing the system to maintain high read performance for common cases while having enhanced correction capability available for rare, more severe error cases.
3Reliability
If primary ECC is allocated to each data block, then error correction capability is provided, but memory capacity is reduced
Solution Approach 1:
Error correction capability is segmented into two layers: primary ECC stored with each data block for immediate correction, and secondary ECC stored separately in dedicated memory regions for enhanced correction. This segmentation allows the system to maintain error correction capability while optimizing memory capacity usage, as secondary ECC is not duplicated with every data block but shared across multiple blocks.
Solution Approach 2:
The secondary ECC regions serve multiple data blocks simultaneously, providing a universal correction resource. Instead of dedicating separate secondary ECC storage to each data block (which would significantly reduce capacity), the system implements shared secondary ECC regions that can correct errors across multiple data blocks, thus maintaining reliability while preserving memory capacity.
Data Source
AI summary
In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.