Memory Error Correction via Segmented ECC Regions
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Solution Overview
Problem
Current memory technologies in automotive electronics face challenges in detecting and correcting errors in dynamic RAM data, as DRAM devices are prone to random changes, and existing error correction methods are not effective for dynamic data.
Innovation Solution
An apparatus that includes an address translator, ECC calculator, concatenator, and data checker to generate and append error correction codes to data elements, allowing for on-the-fly correction of errors during read operations, ensuring data integrity without additional memory or cost impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC check bits are added to each data element for error detection, then data integrity is improved, but memory capacity and cost increase
Solution Approach 1:
The memory space is segmented into data regions and ECC regions. The apparatus divides the memory into separate functional areas where data is stored in one region and its corresponding ECC check bits are stored in another region, rather than combining them. This segmentation allows the system to maintain error detection capability while providing flexible memory management and addressing.
Solution Approach 2:
The patent introduces a new dimension in error correction by separating data and ECC bits spatially across different memory regions. Instead of the traditional approach where ECC bits are appended to each data element in the same memory location, this invention creates a dimensional separation where data resides in data regions and ECC information resides in ECC regions, enabling independent management of data and error correction information.
2Reliability
If traditional ECC methods are used for dynamic RAM data, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The apparatus provides a universal error detection mechanism that works for both dynamic and static data in RAM. The same ECC calculation and verification process applies regardless of whether the data is changing frequently or remaining constant, eliminating the need for different error detection strategies for different data types and simplifying the overall system design.
Solution Approach 2:
The apparatus introduces an intermediary layer between the CPU and the RAM that handles ECC calculation and verification. This intermediary apparatus (comprising the address translator, ECC calculator, concatenator, and data checker) absorbs the complexity of error detection, allowing the rest of the system to operate with simple read/write operations while maintaining robust error detection capability.
3Adaptability or versatility
If address translation is implemented to map data and ECC bits to different memory regions, then memory management flexibility is improved, but processing time increases
Solution Approach 1:
The address translation and ECC region mapping are performed in advance when data is first written to memory. The apparatus pre-calculates the ECC check bits and stores them in the appropriate ECC region, and pre-establishes the address translation mappings. This preliminary action ensures that during subsequent read operations, the system can quickly retrieve both data and ECC bits without performing complex calculations in real-time.
Solution Approach 2:
The apparatus creates and maintains copy-mappings between data regions and ECC regions through the address translator. These pre-established mappings allow the system to quickly locate corresponding ECC bits for any given data location without performing complex address calculations during data access operations, thereby reducing processing time while maintaining flexible memory management.
Data Source
AI summary
The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.