Memory ECC Layout With Shared Parity for Wider Usable Words
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Solution Overview
Problem
Existing memory systems require a large number of parity bits to ensure reliable error correction, which increases memory capacity needs and power consumption, and existing methods to distribute parity bits across multiple words often result in performance drops during read access.
Innovation Solution
A method that distributes parity bits across multiple data words, allowing for error detection and correction within a group of words, where each word includes a payload, an error detection bit, and shared parity bits, enabling single-word read access without performance drops, by using generator polynomials and BCH codes to split and combine parity information effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are added to each data word for error correction, then reliability is improved, but memory capacity and power consumption increase
Solution Approach 1:
The patent segments the traditional monolithic parity structure into multiple components: word-level parity bits (for single-word error correction) and bank-level distributed parity bits (for multi-word error correction). This segmentation allows error correction functionality to be distributed across different granularity levels, reducing the overhead per word while maintaining overall reliability.
Solution Approach 2:
The patent introduces a new dimension of error correction by organizing memory into banks and distributing parity bits across multiple words within the same bank. Instead of adding all parity bits to each individual word, the solution spreads parity information across the bank dimension, allowing G-1 words to share their parity bits with other words in the bank.
2Quantity of substance
If parity bits are distributed across multiple data words, then memory capacity efficiency is improved, but read access performance deteriorates
Solution Approach 1:
The patent implements local quality by providing each data word with its own dedicated word-level parity bits that enable independent error correction for that specific word. This local parity information ensures that single-word reads can be corrected without requiring access to other words, thus maintaining read performance while improving capacity efficiency through shared bank-level parity.
3Reliability
If more parity bits are added per word for higher error correction capability, then reliability is improved, but the number of usable data bits decreases
Solution Approach 1:
The patent makes the parity bits universal by designing them to serve multiple functions: word-level parity bits handle single-word error correction, while the same parity infrastructure supports multi-word error correction when combined with bank-level distributed parity. This multi-functionality allows the system to achieve higher error correction capability without proportionally increasing the number of parity bits per word, thus preserving usable word width.
Data Source
AI summary
Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.