Memory ECC Codeword Routing Across In-Line and Side-Band Channels

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Solution Overview

Problem

Memory devices, particularly DRAM, face challenges in maintaining data integrity due to errors introduced during transmission or storage, which are not adequately addressed by existing error correction methods, especially in applications requiring high reliability such as automotive systems.

Innovation Solution

Implementing error correction coding (ECC) information through both in-line and side-band channels to detect and correct errors in data transmission and storage, utilizing codewords stored within the memory device to ensure data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction coding is implemented to improve data reliability, then data integrity is enhanced, but device complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the error correction system into separate functional components: in-line ECC channels for data transmission and side-band channels for control signals. This segmentation allows independent optimization of each channel type and simplifies the overall system architecture by modularizing the error correction functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dedicated ECC channels as intermediary transmission paths between the memory device and external controller. These intermediary channels carry error correction codewords separately from the main data stream, enabling error detection and correction without interfering with the primary data transmission function.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple channels (in-line and side-band) are used for error correction, then error detection capability is improved, but transmission time increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidtransmission time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs error correction codeword generation and preparation in advance during the data writing process. By pre-computing and storing ECC information in the memory device before read operations, the system eliminates the need for time-consuming real-time error calculation during data retrieval.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic error checking and correction cycles where the memory device continuously monitors data integrity using side-band channels during normal operation. This periodic verification allows error detection without requiring continuous transmission interruptions, maintaining overall system throughput.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250315343A1Methods and devices for error correction
Publication Date: 2025.10.09 LODESTAR LICENSING GROUP LLC
  • US20250315343A1 patent drawing
  • US20250315343A1 patent drawing
  • US20250315343A1 patent drawing

AI summary

Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.