Memory ECC Code Structure for Protected Single-Bit Correction
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Solution Overview
Problem
Existing error correction code (ECC) schemes, such as Hamming codes, have limited error correction capabilities, particularly when single or two-bit errors occur in unprotected locations, leading to erroneous correction operations and potential data loss in memory devices.
Innovation Solution
The implementation of a modified Hamming code (266, 10, 4) that adds an extra parity bit to protect both ECC bits and user data, allowing for the detection and correction of single-bit errors and the detection of three-bit errors, ensuring accurate error correction operations without introducing additional errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Hamming code (265, 9, 3) is used, then the device complexity is lower, but the reliability is insufficient because it cannot correctly handle single or two-bit errors in unprotected locations
Solution Approach 1:
The code structure is segmented into two distinct parts: 256 data bits and 10 ECC bits (9 traditional Hamming bits plus 1 additional parity bit). This segmentation allows the additional bit to specifically handle protection of unprotected locations without affecting the core Hamming code functionality, thereby improving reliability while maintaining manageable complexity.
Solution Approach 2:
The patent extends the traditional Hamming code by adding another dimension - an additional parity bit that operates alongside the existing 9 ECC bits. This dimensional extension transforms the code from (265, 9, 3) to (266, 10, 4), enabling detection and correction of error patterns that were previously unhandleable, thus resolving the reliability issue.
2Reliability
If traditional Hamming code is used, then the manufacturing precision requirements are lower, but erroneous correction operations occur when single or two-bit errors happen in unprotected locations
Solution Approach 1:
The additional parity bit is pre-calculated and stored alongside the traditional 9 ECC bits during the encoding phase. This preliminary action ensures that when decoding occurs, the system already has the necessary information to distinguish between correctable errors and uncorrectable error patterns, preventing erroneous corrections before they can occur.
Solution Approach 2:
The extended ECC structure provides enhanced feedback capability through the 10th parity bit. When errors occur, the combination of the original 9 syndrome bits and the additional parity bit creates a more comprehensive error signature, enabling the decoder to accurately determine whether an error pattern is correctable or should be flagged as uncorrectable, thus improving correction accuracy.
Data Source
AI summary
The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.