Memory Array ECC Mode Layout for Single-Pass SECDED Access
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently storing and accessing error correction information without impacting performance, particularly in architectures that require multiple access passes to retrieve data and parity bits, leading to increased latency and power consumption.
Innovation Solution
A semiconductor memory device architecture that enables single-pass access of error correction code (ECC) information by storing ECC data in both data column planes and an extra column plane, allowing for single error correction and double error detection (SECDED) through a mode register that toggles between operational modes, optimizing data and parity bit retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction information is stored in the array along with associated data, then data integrity and error correction capability are improved, but access latency and power consumption increase due to multiple access passes required
Solution Approach 1:
The memory array is segmented into data regions and dedicated ECC regions, allowing independent access patterns. The ECC circuit is separated from the memory array, enabling parallel error correction operations while data is being accessed, thus reducing the impact on access latency.
Solution Approach 2:
The patent introduces a temporal dimension by implementing asynchronous ECC operations that run in parallel with data access operations. The ECC circuit processes error correction in the background while data is being read or written, eliminating the need for sequential multi-pass access.
2Reliability
If error correction information is stored in the array along with associated data, then data integrity and error correction capability are improved, but power consumption increases due to additional access operations
Solution Approach 1:
ECC data is pre-calculated and stored alongside the main data during the initial write operation. The ECC circuit performs error correction in advance or in parallel, so that when data is accessed, the correction has already been applied or is being applied simultaneously, avoiding additional power-consuming access passes.
Solution Approach 2:
The ECC circuit operates continuously in the background, performing error correction operations without interrupting the main data access flow. This continuous operation allows error correction to happen alongside data operations, maintaining reliability while minimizing additional power consumption.
3Reliability
If multiple access passes are used to retrieve data and parity bits, then complete error correction is achieved, but device complexity and operational overhead increase
Solution Approach 1:
The patent merges the data access path and ECC operation path into a unified parallel architecture. The ECC circuit is integrated with the memory controller to perform error correction simultaneously with data access operations, eliminating the need for separate multi-pass access sequences and reducing operational overhead.
Data Source
AI summary
Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.