Non-Volatile Memory ECC for Skewed Bit Error Rates
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Solution Overview
Problem
Resistive-switching memory technology faces challenges in maintaining data integrity due to non-uniform bit error rates for '0' and '1' states, which can lead to retention problems and program/erase disturbances, affecting the reliability and efficiency of data storage.
Innovation Solution
Implementing bitwise logic or differential algorithms in multiple stages, combined with error correction codes (ECC), to correct bit errors based on measured error rates and skew, ensuring greater correction capacity for the state with higher errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If resistive-switching memory cells are used to provide multiple resistance states for digital memory storage, then storage capacity and density are improved, but non-uniform bit error rates between '0' and '1' states occur, reducing data reliability
Solution Approach 1:
The patent segments the error correction process into multiple stages: first applying a bitwise logic algorithm to correct errors in one state (e.g., '0' state), then applying a differential algorithm to correct errors in the opposite state (e.g., '1' state). This segmented approach allows targeted correction of non-uniform error rates that occur in resistive-switching memory cells, improving data reliability while preserving the high storage capacity provided by multiple resistance states.
Solution Approach 2:
The patent changes the correction parameters dynamically by selecting different algorithms based on the measured bit error rate and the specific state being corrected. When the '0' state has higher error rates, a bitwise logic algorithm with appropriate parameters is applied; when the '1' state has higher error rates, a differential algorithm with adjusted parameters is used. This parameter adaptation resolves the contradiction by maintaining reliability across varying error conditions while preserving storage capacity.
2Device complexity
If standard error correction codes are applied uniformly to all bit states, then implementation simplicity is maintained, but correction effectiveness decreases due to non-uniform error rates between '0' and '1' states
Solution Approach 1:
The patent introduces dynamic adaptability into the error correction system by measuring the bit error rate for each state and selecting/applying different correction algorithms accordingly. Rather than using a static, uniform correction approach, the system dynamically adjusts its correction strategy based on the actual error characteristics of each resistance state, thereby improving correction effectiveness without excessive complexity increase.
Solution Approach 2:
The patent applies local quality by treating '0' state errors and '1' state errors differently with specialized algorithms tailored to each state's error characteristics. The bitwise logic algorithm is optimized for correcting errors in one state, while the differential algorithm is optimized for the other state. This localized correction approach significantly improves error correction effectiveness compared to uniform correction, while the modular structure keeps implementation complexity manageable.
3Reliability
If bitwise logic algorithms are configured to provide greater correction power for one state, then correction effectiveness for that state improves, but the algorithm complexity increases
Solution Approach 1:
The patent segments the correction task into two separate specialized algorithms rather than creating one complex universal algorithm. The bitwise logic algorithm handles correction for one state with optimized simplicity, while the differential algorithm handles the other state. This segmentation reduces the complexity of each individual algorithm while maintaining high correction effectiveness for both states, resolving the contradiction between effectiveness and complexity.
Data Source
AI summary
Improved bit error correction for non-volatile memory can be implemented in multiple stages achieving improved correction capacity. As an example, bit error correction for a set of data can utilize a logic or a differential algorithm applied to one or more copies (N) of the set of data to produce a logic (or differential) output. An error correction code (ECC) can be applied to the logic (or differential) output to produce corrected data that corrects bit errors of the set of data, if any, up to a maximum for the ECC selected. An algorithm can be selected to address measured bit error rates or variations in bit error rates among binary bit states of a non-volatile memory.