Memory ECC Encoding with Split Parity for Lower Computation
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Solution Overview
Problem
The increasing demand for portable electronic devices has led to a rise in the use of semiconductor-based memory systems, which face challenges in error correction due to increased data integrity issues and error rates, particularly in non-volatile memory cells, where the complexity of encoder and decoder designs for error correction codes is high, and the computation required for generating parity bits is substantial.
Innovation Solution
The implementation of an error correction code apparatus and method that reduces the complexity of encoder and decoder designs by dividing parity bits into two groups using a combination of matrix multiplication and exclusive OR operations, based on polynomials determined by a second matrix, to generate a codeword for storage in non-volatile memory cells, thereby reducing the number of matrix multiplications and computation required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction code encoding is used, then data integrity is maintained, but the complexity of encoder and decoder designs increases and computation required for generating parity bits is substantial
Solution Approach 1:
The parity bits are divided into two separate groups: first parity bits generated by matrix multiplication of the data bits with a first matrix, and second parity bits generated by XOR operations between the data bits and the first parity bits. This segmentation allows the encoder to use simpler operations for the second parity group while maintaining the same error correction capability, thereby reducing overall system complexity.
Solution Approach 2:
The patent changes the mathematical operations used for parity bit generation. Instead of using a single complex matrix multiplication for all parity bits, it uses matrix multiplication only for the first parity group and XOR operations for the second parity group. This parameter change in the mathematical approach reduces computational complexity while preserving data integrity.
2Reliability
If traditional error correction code encoding is used, then data integrity is maintained, but the computation required for generating parity bits is substantial
Solution Approach 1:
By dividing parity bits into two groups with different generation methods, the patent reduces the computational burden. The first parity group uses matrix multiplication (computationally intensive) while the second parity group uses XOR operations (computationally simpler), thereby reducing total power consumption while maintaining error correction capability.
Solution Approach 2:
The patent substitutes matrix multiplication with XOR operations for generating the second parity group. This replacement of a computationally heavy operation with a simpler logical operation reduces the computational power required while maintaining the same level of error detection and correction.
Data Source
AI summary
Error correction code apparatuses and memory systems are disclosed. The apparatus may include an encoder configured to generate a first result by multiplying bits of the data by a first matrix, divides parity bits into a first parity group obtained by multiplying the first result by a second matrix and a second parity group obtained by an exclusive OR operation of the first result and the first parity group, based on a plurality of polynomials determined based on the second matrix, and multiply the first result and the second matrix to generate one or more first parity bits in the first parity group, perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group, and generate a codeword having the bits of the data bits and the parity bits.