Memory ECC Using Long and Short Sub-Word Lines for Driver-Failure Resilience
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Solution Overview
Problem
As semiconductor memory devices increase in capacity, it becomes increasingly difficult to fabricate memory devices without defective memory cells, necessitating the use of redundant memory cells and error correction circuits to address errors during operations, but existing error correction methods struggle with efficiency and effectiveness, especially when sub-word line drivers fail.
Innovation Solution
A memory system design that includes a memory controller for continuous transfer of codewords, utilizes long and short sub-word lines, and employs error correction code generation circuits to enhance error correction capabilities by dividing codewords into smaller units and storing error correction codes differently based on sub-word line types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are stored in memory cells coupled to long sub-word lines, then error correction capability is improved, but when sub-word line drivers fail, the entire row becomes unusable
Solution Approach 1:
The patent divides the error correction code storage into two separate locations: memory cells coupled to long sub-word lines and memory cells coupled to short sub-word lines. This segmentation ensures that if one set of sub-word line drivers fails, the error correction codes stored in the other location remain accessible, maintaining system reliability.
Solution Approach 2:
Different types of memory cells are used for different purposes within the same row: some memory cells store data while others store error correction codes. Memory cells coupled to short sub-word lines are specifically designated for storing error correction codes, while memory cells coupled to long sub-word lines store data. This local differentiation optimizes both error correction capability and fault tolerance.
2Manufacturing precision
If redundant memory cells are used to replace defective memory cells, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The patent makes short sub-word lines and their associated memory cells serve dual purposes: they can be used for normal data storage operations and simultaneously serve as storage locations for error correction codes. This multi-functionality eliminates the need for completely separate redundant memory structures, reducing overall device complexity while maintaining manufacturing yield improvements.
3Reliability
If ECC circuits are used to correct errors, then data integrity is improved, but operation time increases
Solution Approach 1:
Error correction codes are generated and stored in the memory cells during the initial write operation, rather than being generated later during read operations. This preliminary action allows the ECC circuit to perform only verification and correction tasks during reads, significantly reducing operation time while maintaining data integrity.
Data Source
AI summary
A memory system includes a plurality of memories, each including a plurality of data input terminals; and a memory controller configured to continuously transfer a first codeword and a second codeword to the data input terminals of the memories during a write operation.