Memory System ECC Switching for Reed-Solomon Error Recovery

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Solution Overview

Problem

Existing memory systems face inefficiencies when combining on-die error correction capabilities with Reed-Solomon error correction, as on-die ECC can introduce additional errors that the RS decoder cannot correct, leading to uncorrectable errors in the data.

Innovation Solution

A memory system is configured to dynamically disable on-die error correction (ECC) when uncorrectable errors are detected, allowing for subsequent re-reads using only Reed-Solomon (RS) error correction to correct correctable errors before transmitting data to the host system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If on-die ECC is enabled to correct errors in data, then error correction capability is improved, but additional errors may be introduced that cannot be corrected by Reed-Solomon decoding

Engineering Contradiction:
Improveerror correction capabilityVSAvoidadditional errors introduced by on-die ECC
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements dynamic control of on-die ECC by enabling it for first read operations and disabling it for second read operations. This dynamic switching allows the system to adapt to different operational contexts: when on-die ECC is enabled, it can correct certain errors; when disabled, it prevents introducing additional uncorrectable errors, allowing Reed-Solomon decoding to handle the errors successfully.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter of on-die ECC from a static enabled state to a dynamically adjusted state. By modifying the ECC enablement parameter based on read operation sequence and error patterns, the system optimizes the balance between error correction capability and harm reduction, achieving better overall data integrity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If on-die ECC is always enabled to maximize error correction, then reliability is improved, but device complexity and operational overhead increase

Engineering Contradiction:
Improveerror detection and correctionVSAvoiderror correction management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs periodic action by implementing a structured read operation sequence: first read operations with on-die ECC enabled, followed by second read operations with on-die ECC disabled. This periodic switching pattern simplifies error correction management by following a predetermined sequence rather than requiring complex real-time decisions, reducing operational overhead while maintaining reliability.

Inventive Principle:
Principle #19Periodic action

3Reliability

If on-die ECC is used to correct errors in real-time, then data integrity is improved, but processing time increases due to additional correction attempts

Engineering Contradiction:
Improvedata integrityVSAvoidtime for error correction operations
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by enabling on-die ECC during first read operations to proactively correct errors before they propagate. By performing error correction in advance during the first read attempt, the system reduces the need for repeated correction cycles, thereby minimizing time loss while ensuring data integrity is established early in the process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250239320A1Error correction disablement by a memory system
Publication Date: 2025.07.24 MICRON TECHNOLOGY INC
  • US20250239320A1 patent drawing
  • US20250239320A1 patent drawing
  • US20250239320A1 patent drawing

AI summary

Methods, systems, and devices for error correction disablement by a memory system are described. The method may include a memory system reading, at a first time, data from one or more memory cells of a memory device and disabling a first error correction capability based on the data comprising one or more errors of a first type. Further, the method may include the memory system reading, at a second time, the data and transmitting the data to a host device based on the data not comprising the one or more errors of the first type.