Adaptive ECC Symbol Mapping in Memory Controllers for Burst Errors

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Solution Overview

Problem

Current memory systems face limitations in error correction capabilities, particularly in volatile memory devices like DRAM, which can lead to data loss and reduced reliability due to high error bit rates during burst operations.

Innovation Solution

A memory controller with an error correction code (ECC) engine that adaptively constructs codewords based on device information, including mapping information and error tendency data, to increase error detection and correction capabilities, ensuring that the number of error bits in symbols is within a reference limit, thereby enhancing reliability and serviceability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction capability is increased by adding more error detection/correction bits, then reliability improves, but device complexity and overhead increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidECC engine complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ECC engine dynamically adjusts error correction strategies based on real-time error patterns detected in memory devices. The system monitors error bits across multiple symbols and adaptively selects correction methods, transitioning between different error correction modes as error conditions change, rather than using a fixed complex ECC scheme throughout.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters of the ECC engine based on error characteristics. When error bits exceed thresholds in multiple symbols, the engine modifies correction parameters such as increasing check bits or changing correction algorithms, allowing flexible adaptation without permanent structural complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the number of error detection/correction bits is increased to handle hard fail conditions, then error correction capability improves, but loss of information increases due to more overhead bits

Engineering Contradiction:
Improvehard fail correction capabilityVSAvoiddata overhead
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The ECC engine applies partial error correction by focusing only on the specific symbols containing error bits rather than processing all data uniformly. When error bits are detected in fewer than a threshold number of symbols, the system applies targeted correction only to affected portions, avoiding the overhead of comprehensive error correction on entire data blocks.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The data is divided into multiple symbols, and error correction is applied selectively to individual symbols based on error detection results. This segmentation allows the system to apply error correction overhead only where necessary, rather than adding overhead to all data regardless of error conditions.

Inventive Principle:
Principle #1Segmentation

3Reliability

If adaptive symbol construction based on mapping information is implemented, then error correction capability improves, but device complexity increases

Engineering Contradiction:
Improveadaptive error correctionVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Mapping information is pre-established during system initialization or memory device configuration, defining optimal symbol constructions for different error patterns. This preliminary setup allows the ECC engine to quickly reference and apply appropriate mappings during operation without performing complex real-time analysis, reducing operational complexity while maintaining adaptive error correction capability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11068347B2Memory controllers, memory systems including the same and memory modules
Publication Date: 2021.07.20 SAMSUNG ELECTRONICS CO LTD
  • US11068347B2 patent drawing
  • US11068347B2 patent drawing
  • US11068347B2 patent drawing

AI summary

A memory controller configured to control a memory module including a plurality of memory devices which constitute a first channel and a second channel includes an error correction code (ECC) engine, and a control circuit configured to control the ECC engine. The ECC engine is configured to generate a codeword including a plurality of symbols by adaptively constructing, based on device information including mapping information, each of the plurality of symbols from a predetermined number of data bits received via a plurality of input/output pads of each of the plurality of memory devices, and transmit the codeword to the memory module. The mapping information indicates whether each of the plurality of input/output pads is mapped to the same symbol among the plurality of symbols or different symbols among the plurality of symbols. Each of the plurality of symbols corresponds to a unit of error correction of the ECC engine.