Semiconductor Memory ECC Engine for Multi-Bit Syndrome Correction

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Solution Overview

Problem

The increasing bit errors and decreasing yield in DRAM devices due to reduced fabrication design rules affect the performance and reliability of semiconductor memory devices.

Innovation Solution

An error correction code (ECC) engine is integrated into semiconductor memory devices, utilizing a primitive polynomial-based ECC encoder and decoder to generate and correct syndromes for single, adjacent, and non-adjacent bit errors in memory cells, enhancing error correction efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fabrication design rules are reduced to increase memory density, then memory capacity is improved, but bit error rate increases and yield decreases

Engineering Contradiction:
Improvememory capacityVSAvoidbit error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by generating syndromes in advance during the write operation, before data is read back. The ECC encoder computes syndromes based on the data being written and stores them alongside the main data. When reading, these pre-computed syndromes are immediately available for error detection and correction, eliminating the need to recompute them and reducing read latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses syndromes as an intermediary element between the stored data and the error correction process. The syndrome acts as a mediator that contains encoded information about potential errors in the data, allowing the ECC decoder to identify and correct errors without directly analyzing the entire data pattern. This intermediary approach enables efficient error detection and correction.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If traditional ECC methods are used, then single bit errors are corrected, but adjacent and non-adjacent bit errors cannot be effectively corrected

Engineering Contradiction:
Improvesingle bit error correctionVSAvoiderror pattern coverage
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements universality by designing a single syndrome generation and application mechanism that handles multiple error patterns (single bit errors, adjacent bit errors, and non-adjacent bit errors). The same ECC encoder and decoder infrastructure is used for all error types, with the syndrome automatically adapting to the specific error pattern detected. This multi-functional approach eliminates the need for separate correction circuits for different error types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies parameter changes by modifying the syndrome generation process to account for different error patterns. The ECC encoder generates syndromes that encode information about multiple possible error types. During decoding, the syndrome values are analyzed to determine which error pattern is present, and the correction process adjusts its parameters accordingly to handle the specific error type detected.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If comprehensive error correction for all error patterns is implemented, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidECC circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies discarding and recovering by selectively applying syndromes based on the detected error pattern. The ECC decoder analyzes the syndrome to determine which type of error occurred (single bit, adjacent bits, or non-adjacent bits) and only applies the corresponding correction. This selective approach discards unnecessary correction operations for error patterns that don't match, reducing computational complexity while maintaining comprehensive error correction capability.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS20260111307A1Error correction code engine of semiconductor memory device and semiconductor memory device
Publication Date: 2026.04.23 SAMSUNG ELECTRONICS CO LTD
  • US20260111307A1 patent drawing
  • US20260111307A1 patent drawing
  • US20260111307A1 patent drawing

AI summary

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data based on a primitive polynomial and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome and corrects at least one error bit in the read codeword based on the syndrome by respectively applying different syndromes to a single bit error in the read codeword, adjacent bit errors and non-adjacent bit errors occurring in non-adjacent two memory cells in the target page. The ECC decoder generates the different syndromes based on a parity check matrix generated as a function of the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.