Semiconductor Memory ECC Test Circuit Error Classification
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing test time overhead and improving test accuracy, particularly in distinguishing between correctable and uncorrectable errors during parallel bit tests.
Innovation Solution
Incorporating an error correction code (ECC) engine and a test circuit that performs parallel bit tests, subtracts error bits correctable by the ECC, and records results in separate fail address memories to differentiate between correctable and uncorrectable errors, thereby reducing test time and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional test method is used to test the memory cell array, then the test can identify errors, but the test time overhead is increased and test accuracy is reduced due to inability to distinguish correctable from uncorrectable errors
Solution Approach 1:
The test result data is segmented into two distinct categories: correctable errors and uncorrectable errors. The test circuit separates the counting process by maintaining different error counters (first error counter for correctable errors, second error counter for uncorrectable errors), allowing precise classification and reporting of error types rather than treating all errors uniformly.
Solution Approach 2:
The ECC engine performs preliminary error correction on the test result data before the test circuit counts and classifies errors. By pre-correcting correctable errors using the ECC engine, the test system can efficiently distinguish between errors that were corrected (indicating good memory cells) and errors that remain (indicating uncorrectable failures), thereby reducing unnecessary test overhead.
2Loss of information
If all error bits are transmitted to the outside as fail bits, then comprehensive error information is provided, but the number of transmitted bits increases and test efficiency decreases
Solution Approach 1:
The invention extracts and separates correctable error information from uncorrectable error information. The test circuit uses the ECC engine to identify and extract correctable errors, then only transmits uncorrectable errors (which truly represent failures) to the outside world. This extraction process eliminates redundant transmission of correctable error data while preserving critical failure information.
Solution Approach 2:
Different quality levels are applied to different error types in the transmission process. Correctable errors are handled with higher quality processing (corrected by ECC engine before counting), while uncorrectable errors are flagged for transmission. The result signal transmission is optimized by only including uncorrectable error information, providing locally optimized information quality for each error category.
3Quantity of substance
If the test circuit counts all error bits without ECC correction, then the complete error count is obtained, but uncorrectable errors may be misinterpreted as correctable errors
Solution Approach 1:
The ECC engine performs preliminary correction of correctable errors before the test circuit counts errors. This preliminary action ensures that when the test circuit counts errors in the corrected test result data, it only counts uncorrectable errors, preventing misclassification. The sequence of ECC correction followed by error counting guarantees reliable error classification.
Solution Approach 2:
The ECC engine acts as an intermediary between the memory cell array and the test circuit's error counting function. It processes the test result data first, correcting correctable errors, and then passes the corrected data to the test circuit for accurate counting. This intermediary processing step ensures that the test circuit receives pre-processed data where correctable errors have been eliminated, enabling accurate distinction between correctable and uncorrectable errors.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of dynamic memory cells, an ECC engine configured to correct at least one error in a read data from the memory cell array, and a test circuit which performs a test on the memory cell array in a test mode of the semiconductor memory device by writing a test pattern data in the memory cell array and by reading, from the memory cell array, test result data corresponding to the test pattern data. When the test result data includes at least one error bit, the test circuit subtracts a second number from a first number of the at least one error bit and is configured to output the subtracted result to an outside of the semiconductor memory device. The second number corresponds to a number of error bits that the ECC engine is capable of correcting.