Memory ECC Word Mapping for Correlated Transfer Errors
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Solution Overview
Problem
High-speed memory interfaces face increased failure rates due to clock jitter and inter symbol interference, exceeding the capability of contemporary error correction codes (ECC) designed for random errors, leading to uncorrectable and undetectable faults.
Innovation Solution
A split ECC symbol code word mapping that constructs an ECC word using bits from different memory device transfers, ensuring that even multiple simultaneous errors are correctable and detectable without the need for additional pins or performance-degrading cyclic redundancy check (CRC) methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contemporary ECC schemes are used for high-speed memory interfaces, then random error detection and correction is provided, but they fail to address correlated errors caused by clock jitter and inter symbol interference
Solution Approach 1:
The patent segments the ECC protection scope from traditional device-level to pin-level or group-level. By dividing the error protection into smaller, more granular units (individual pins or pin groups), the system can apply ECC specifically to affected pins experiencing correlated errors from clock jitter, while maintaining standard ECC for other pins. This segmentation allows targeted error correction adaptability without requiring complete system redesign.
Solution Approach 2:
The patent introduces dynamic error correction capabilities where the ECC mechanism can adapt its behavior based on error patterns detected in high-speed interfaces. The system dynamically identifies pins experiencing correlated errors and applies appropriate correction strategies, transitioning from static device-level ECC to dynamic pin-level ECC that responds to real-time error conditions caused by clock jitter and inter symbol interference.
2Reliability
If CRC coding is used to address correlated errors, then error detection capability is improved, but additional pins are required and memory performance is dramatically affected due to re-try operations
Solution Approach 1:
Instead of applying CRC to all data transfers (which would cause performance degradation), the patent applies error correction only to the specific pins or pin groups experiencing correlated errors. This partial application of error correction avoids the need for extensive re-try operations on healthy pins, maintaining memory performance while providing targeted protection against clock jitter effects.
Solution Approach 2:
The patent uses lightweight ECC mechanisms for pin-level error correction instead of heavy CRC implementations. The pin-level ECC provides sufficient error detection and correction for the specific correlated error patterns without requiring the overhead of CRC, avoiding both additional pin requirements and performance-detracting re-try operations.
3Reliability
If pin-level or group-level ECC is applied to address clock jitter effects, then coverage for correlated errors is maximized, but device complexity increases
Solution Approach 1:
The patent segments the memory interface into pin-level or group-level units for ECC application, allowing granular error protection. This segmentation enables the system to apply complex error correction only where needed (on pins experiencing clock jitter effects) while using simpler mechanisms elsewhere, managing device complexity through selective application rather than universal complexity.
Solution Approach 2:
The patent creates a universal ECC framework that can operate at multiple levels (device-level for random errors, pin-level or group-level for correlated errors). This multi-functional ECC system handles both random and correlated error patterns using a unified approach, reducing the need for separate complex error correction paths and managing overall device complexity.
Data Source
AI summary
A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers.