Memory Error Correction via Dual-Dimensional ECC Triangulation
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Solution Overview
Problem
Current memory systems face challenges in detecting and correcting errors, particularly in RAID memory systems, where a complete DIMM failure can cause the entire system to fail, and existing error correction techniques increase costs, complexity, and reduce available memory, while being inefficient in handling secondary chip errors.
Innovation Solution
The implementation of a memory system that uses two independent error correction codes (one applied horizontally and one vertically) in conjunction with triangulation to isolate and correct up to a full DIMM failure and secondary chip errors, allowing for concurrent repair and maintaining system operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction techniques are used in RAID memory systems, then error detection capability is improved, but system complexity and cost increase
Solution Approach 1:
The patent divides the error correction approach into two independent codes: a first error correction code applied horizontally to data elements within a memory device, and a second error correction code applied vertically to data elements across multiple memory devices. This segmentation allows each code to handle specific error scenarios independently, improving detection capability without requiring a single complex correction mechanism.
Solution Approach 2:
The patent introduces a two-dimensional error correction framework by applying error correction codes in both horizontal and vertical dimensions. The first ECC handles horizontal errors within devices, while the second ECC handles vertical errors across devices, creating a dimensional approach that enhances reliability without proportionally increasing complexity.
2Reliability
If more memory is allocated for error correction, then fault tolerance is improved, but available memory capacity is reduced
Solution Approach 1:
The patent applies different error correction strategies to different locations and error scenarios. The first ECC is applied locally to data elements within each memory device, while the second ECC is applied to data elements across multiple devices. This localized approach ensures that error correction overhead is distributed efficiently, maintaining fault tolerance while preserving maximum available memory capacity for actual data storage.
3Reliability
If existing error correction methods are used, then single errors can be detected, but secondary chip errors cannot be handled efficiently
Solution Approach 1:
The patent implements preliminary error correction by applying the first ECC to data elements within each memory device before they are accessed, and the second ECC to data elements across multiple devices. This preliminary correction framework is already in place when errors occur, enabling rapid detection and correction of both single errors and secondary chip errors without requiring complex real-time analysis.
Solution Approach 2:
The patent creates redundant error correction capability by implementing two independent error correction codes instead of relying on a single correction mechanism. The first ECC provides a copy of error protection at the device level, while the second ECC provides a copy at the cross-device level, enabling efficient handling of multiple error scenarios including secondary chip errors.
Data Source
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AI summary
A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.