Memory ECC Coding with Variable Redundancy Across Channels
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Solution Overview
Problem
Memory devices face high error rates during data reading and writing due to channel characteristics, which increases hardware complexity and decreases code rate, necessitating an effective error-control code (ECC) encoding and decoding scheme.
Innovation Solution
A memory device with a processor that adjusts redundant information rates by generating codewords based on previous information, using ECC encoding and decoding to reduce error rates, particularly in multi-level cell (MLC) or multi-bit cell (MBC) devices, by employing a decoder to estimate messages and combine data to generate corrected codewords, and an encoder to store these codewords with optimized error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC encoding and decoding schemes are used, then error correction capability is provided, but hardware complexity increases and code rate decreases due to high error rates in memory channels
Solution Approach 1:
The patent segments the data storage into multiple channels (first channel and second channel) with different error rates. Each channel is assigned a different code rate, allowing the system to optimize error correction resources according to actual channel conditions rather than using uniform high-rate ECC across all data paths.
Solution Approach 2:
The patent applies different code rates to different channels based on their specific error characteristics. The first channel with higher error rate receives a higher code rate (more redundant information), while the second channel with lower error rate receives a lower code rate, optimizing overall system performance rather than applying a one-size-fits-all approach.
2Reliability
If higher code rate is used to overcome high error rates, then error correction capability improves, but the proportion of redundant information increases reducing effective data throughput
Solution Approach 1:
The patent divides the data transmission into multiple channels and assigns different code rates to each segment. This allows the system to achieve necessary error correction capability in high-error channels without unnecessarily reducing the code rate for all data, thereby maintaining higher overall productivity.
Solution Approach 2:
The patent dynamically adjusts the code rate parameter based on channel characteristics. By changing the code rate from uniform to variable across channels, the system optimizes the balance between reliability and productivity, ensuring sufficient error correction where needed while maximizing data throughput where error rates are lower.
3Ease of manufacture
If uniform ECC scheme is applied to all data channels, then implementation is simplified, but error correction efficiency decreases when channels have different error characteristics
Solution Approach 1:
The patent segments channels based on their error characteristics and applies differentiated ECC schemes to each segment. This maintains relative implementation simplicity while significantly improving error correction efficiency compared to a uniform approach, as each channel receives error correction optimized for its specific conditions.
Solution Approach 2:
The patent applies the principle of local quality by tailoring the ECC scheme to each channel's specific error characteristics. The first channel receives a ECC configuration optimized for higher error rates, while the second channel receives a different configuration suited to its lower error rate, thereby optimizing overall error correction efficiency.
Data Source
AI summary
Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.