Memory ECC Using Vulnerable Row Data to Prevent Silent Corruption
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Solution Overview
Problem
As memory devices such as DRAMs increase in integration and speed, the bit error rate rises, leading to a decrease in yield and the occurrence of Silent Data Corruption (SDC) due to errors exceeding the error correction capability of existing ECC circuits.
Innovation Solution
Incorporating an eraser detector to identify vulnerable rows, an ECC engine to correct errors based on vulnerable row data, and a flag generator to indicate decoding states, enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the integration and speed of memory devices are increased, then the performance is improved, but the bit error rate increases and reliability decreases
Solution Approach 1:
The patent applies preliminary action by pre-storing vulnerable row data that identifies locations of estimation errors corresponding to vulnerable rows before actual data reading occurs. This advance preparation enables the ECC engine to quickly locate and correct errors without increasing operational speed, thereby maintaining high performance while improving reliability through proactive error positioning.
2Reliability
If the ECC circuit corrects errors in data, then the reliability is improved, but Silent Data Corruption occurs when errors exceed correction capability
Solution Approach 1:
The patent implements feedback by generating a decoding flag based on vulnerable row data, error information, and corrected data. This feedback mechanism allows the system to monitor whether errors have been successfully corrected or if they exceed correction capability, preventing Silent Data Corruption by providing visible indication of uncorrectable errors through the decoding flag that can trigger retransmission or error handling procedures.
Solution Approach 2:
The vulnerable row data acts as an intermediary that bridges the gap between raw data and error correction processing. By introducing this intermediate layer that pre-identifies vulnerable locations, the system enhances the ECC circuit's ability to detect and correct errors while maintaining awareness of error patterns that may exceed correction capabilities, thus preventing undetected data corruption.
3Measurement precision
If vulnerable row data is stored and used for error correction, then the error detection accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent applies merging by integrating the vulnerable row data storage function directly into the existing memory structure and combining the error detection and correction processes into a unified ECC engine operation. This consolidation achieves high error detection accuracy without proportionally increasing device complexity, as the vulnerable row data is stored alongside regular data and processed through the existing ECC infrastructure with minimal additional components.
Data Source
AI summary
A memory device includes a memory cell array that includes a plurality of memory cells disposed in a plurality of rows, an eraser detector that stores vulnerable row data including a location of an estimation error corresponding to a vulnerable row among the plurality of rows, an error correction code (ECC) engine that decodes first data read from the memory cell array based on the vulnerable row data to generate information on a first error included in the first data in response to a read command and corrects the first error to generate second data, and a flag generator that generates a decoding flag indicating a decoding state of the ECC engine based on the vulnerable row data, the information on the first error, and the second data.