Memory Subsystem ECC Adaptation Based on Wear Level
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory sub-systems use a fixed error correction code based on the worst-case scenario, leading to excessive parity bits at the beginning of their operating life, which reduces storage efficiency and increases wear due to unnecessary parity data writing.
Innovation Solution
Adaptive error correction codes are implemented based on the wear and usage of the memory sub-system, increasing the number of parity bits over time as the rate of errors increases, using a polar encoder and decoder to adjust the code rate and parity bit storage accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed error correction code based on worst-case scenario is used, then reliability is improved, but storage efficiency deteriorates due to excessive parity bits
Solution Approach 1:
The patent implements dynamic adjustment of error correction code parameters (code rate, number of parity bits) based on the wear level of the memory sub-system. As wear increases, the system transitions from lower redundancy codes to higher redundancy codes, optimizing the balance between reliability and storage efficiency at each stage of the memory lifecycle
Solution Approach 2:
The system changes key parameters of the error correction code (code rate R, number of parity bits) according to wear indicators such as program/erase cycle counts. This parameter adaptation allows the system to use minimal parity bits when the memory is new (high storage efficiency) and increase parity bits when wear increases (high reliability), resolving the contradiction between these two objectives
2Reliability
If excessive parity bits are written at the beginning of operating life, then reliability is improved, but device wear increases due to unnecessary writing
Solution Approach 1:
The system adjusts the number of parity bits based on wear indicators (program/erase cycle counts). When the memory sub-system is new and wear is low, the system uses a lower code rate with fewer parity bits, reducing unnecessary writes. As wear increases, the system increases the code rate and parity bit count to maintain reliability, thus optimizing endurance across the device lifecycle
Solution Approach 2:
The error correction strategy dynamically adapts to the current wear state of the memory sub-system. The controller monitors wear indicators and adjusts ECC parameters in real-time, transitioning from aggressive error correction (when new) to more conservative error correction (when worn), thereby extending device endurance while maintaining reliability
3Quantity of substance
If adaptive error correction codes are implemented, then storage efficiency is improved, but device complexity increases
Solution Approach 1:
The system implements a feedback mechanism where the controller monitors wear indicators (program/erase cycle counts, error rates) and uses this information to adjust error correction code parameters. This feedback loop enables adaptive optimization of storage efficiency while maintaining reliability, with the complexity managed through systematic wear tracking and pre-defined code selection criteria
Data Source
AI summary
Systems and methods are disclosed that are of retrieving, by a processing device, a codeword stored at a memory sub-system, determining parity data of the codeword, generating additional parity bits based on one or more bits of the parity data of the codeword, and generating host data by decoding the codeword using the additional parity bits.