Memory Controller ECC Switching for Worn Flash Areas
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Solution Overview
Problem
As memory devices miniaturize and become multivalued, the probability of errors increases, necessitating stronger error correction codes, but existing methods to enhance error correction capability, such as increasing parity data size, lead to increased circuit complexity and reduced user data capacity.
Innovation Solution
A memory controller that dynamically adjusts the error correction encoding method based on the fatigue degree of memory areas, switching to higher error correction capabilities when necessary while maintaining a total parity sum below a threshold, thereby improving error correction without increasing circuit scale or data size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but circuit scale increases and user data capacity decreases
Solution Approach 1:
The patent implements dynamic adjustment of error correction capability by switching between different encoding methods (first encoding method with lower capability and second encoding method with higher capability) based on the fatigue degree of memory areas. This allows the system to adapt error correction strength to actual needs rather than using a fixed high-capability encoding for all data, thereby reducing overall circuit complexity while maintaining reliability where necessary.
Solution Approach 2:
The patent applies different encoding methods to different memory areas based on their individual fatigue degrees. Memory areas with higher fatigue receive stronger error correction (second encoding method), while areas with lower fatigue use weaker error correction (first encoding method). This localized approach ensures error correction capability is applied precisely where needed, avoiding unnecessary circuit complexity in areas that don't require it.
2Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but the capacity of user data to be stored decreases
Solution Approach 1:
The system dynamically adjusts the amount of parity data required based on the fatigue degree of memory areas. When memory areas are in good condition (low fatigue), the system uses encoding methods that require less parity data, thereby maximizing user data capacity. When fatigue increases, the system switches to encoding methods with more parity data only for those specific areas, maintaining error correction capability without unnecessarily reducing overall storage capacity.
Solution Approach 2:
Different portions of the memory system are assigned different encoding methods based on their fatigue characteristics. This ensures that parity overhead is incurred only where necessary to maintain reliability, rather than applying uniform high-level error correction across the entire memory capacity, thus preserving maximum user data capacity in healthy memory regions.
3Reliability
If stronger error correcting codes are used to handle increased error probability in miniaturized memory, then error correction capability is improved, but circuit complexity and implementation difficulty increase
Solution Approach 1:
The patent implements a dynamic encoding method selection mechanism that switches between a first encoding method (simpler circuit implementation) and a second encoding method (more complex but higher capability) based on real-time monitoring of memory fatigue. This allows the system to use simpler circuits during normal operation and only engage more complex error correction circuits when actually needed, reducing overall circuit complexity requirements.
Solution Approach 2:
The system applies complex error correction algorithms only to specific memory areas that exhibit high fatigue and require enhanced protection, while leaving other areas with simpler encoding. This localized application of complex algorithms reduces the overall circuit complexity burden compared to implementing strong error correction across the entire memory system.
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.