ECC Memory Write-Mask Pipelining for Lower tCCD Latency
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Solution Overview
Problem
Semiconductor memory devices face increased susceptibility to soft errors due to reduced voltage levels and smaller memory cell sizes, leading to errors from charge leakage and weak cells, which can result in random single bit errors, and error correction codes (ECC) used to compensate for these errors often decrease memory performance by increasing operation time.
Innovation Solution
The implementation of a memory system with a write driver, data sense amplifier, error control code circuit, and control circuit that allows for pipelining of consecutive write mask operations, enabling concurrent execution of operations and reducing the column-to-column delay (tCCD) by pre-charging local input-output lines during error correction processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is used to compensate for data errors in memory cells, then data integrity is improved, but the time required for memory operations increases
Solution Approach 1:
The patent pre-charges local input-output lines before memory operations are completed. By performing this preparation action in advance, the system reduces the column-to-column delay (tCCD) for subsequent operations, thereby decreasing overall memory operation time while maintaining ECC error correction functionality
Solution Approach 2:
The patent pipelines consecutive write mask operations, allowing them to execute concurrently rather than sequentially. This continuous overlapping of operations maintains productive work during what would otherwise be idle periods, reducing total execution time while preserving data integrity through ECC
2Reliability
If consecutive write mask operations are executed sequentially, then error correction accuracy is maintained, but memory performance decreases
Solution Approach 1:
The control circuit pre-charges local input-output lines before subsequent memory operations begin. This preliminary preparation reduces the column-to-column delay (tCCD), enabling faster execution of pipelined write mask operations while maintaining error correction accuracy through the ECC circuit
Solution Approach 2:
The patent dynamically pipelines consecutive write mask operations, allowing the memory system to adaptively overlap operation execution. This dynamic approach enables the system to maintain error correction accuracy while improving memory performance through concurrent operation execution
Data Source
AI summary
Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.