Memory ECC Pipelining for Faster Write Mask Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor memory sizes shrink and voltage levels decrease, memory devices become more prone to errors due to reduced charge margins and weak cells, leading to increased soft errors and variable refresh times, which can be exacerbated by ECCs that increase operation time, thereby reducing memory performance.
Innovation Solution
Implementing pipelined error correction coding (ECC) by concurrently executing multiple memory operations, including read and write mask operations, to reduce the overall execution time of write mask operations and enhance memory performance while maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is used to correct data errors in memory cells, then data integrity is improved, but the time required for memory operations increases
Solution Approach 1:
The patent pre-charges local input-output lines before actual data transfer operations. This preliminary action prepares the circuit paths in advance, reducing the overall operation time when ECC processing is performed, thereby mitigating the time penalty associated with error correction
Solution Approach 2:
The patent implements variable refresh times for memory cells based on their individual charge leakage characteristics. By periodically refreshing weak cells more frequently and strong cells less frequently, the system maintains data integrity while optimizing the timing of ECC operations to minimize performance impact
2Area of stationary object
If feature sizes of semiconductor memory are reduced to produce smaller memory components, then memory capacity per area is improved, but the margin of error for detecting data state decreases
Solution Approach 1:
The patent performs preliminary charging of memory cells with optimized voltage levels and durations tailored to each cell's characteristics. This preliminary action ensures that even in reduced-feature-size memory cells, sufficient charge margin is established before read operations, improving detection precision despite smaller cell sizes
Solution Approach 2:
The patent dynamically adjusts charging parameters such as voltage level, charging duration, and refresh timing based on individual cell characteristics and environmental conditions. This parameter optimization compensates for reduced charge margins in smaller memory cells, maintaining reliable data state detection
3Use of energy by stationary object
If voltage levels provided to semiconductor memory are reduced to limit power consumption, then power consumption is reduced, but memory cells become more prone to soft errors
Solution Approach 1:
The patent optimizes voltage levels and charging durations based on individual cell characteristics and operational conditions. By dynamically adjusting these parameters, the system maintains sufficient charge margins for reliable operation at lower voltage levels, reducing power consumption while mitigating susceptibility to soft errors and alpha particle interactions
Data Source
AI summary
Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.