Memory Error Check and Scrub for On-Die ECC Visibility
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Solution Overview
Problem
Traditional memory subsystems fail to detect and correct errors effectively within DRAM devices due to on-die ECC, leading to undetected error accumulation, as system-level ECC lacks insight into internal error correction processes.
Innovation Solution
Implementing an error check and scrub (ECS) mode in memory devices that enables internal error monitoring and correction, allowing for error counting and transparency of error information to the host system, using on-die ECC logic to correct single bit errors and store error counts in registers for system-level ECC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC logic is implemented to correct single bit errors, then error correction capability is improved, but error transparency to the host system deteriorates
Solution Approach 1:
An error information register is introduced as an intermediary component between the on-die ECC logic and the host system. This register stores error information (such as error counts and error addresses) generated by the ECC logic, making this information visible and accessible to the host system without interfering with the error correction process. The register acts as a mediator that preserves error transparency while maintaining the autonomous error correction capability of the on-die ECC logic.
2Reliability
If system level ECC is used to detect errors, then error detection capability is improved, but insight into internal error correction processes is lost
Solution Approach 1:
The error monitoring function is segmented into two distinct parts: (1) on-die ECC logic that handles error detection and correction at the memory device level, and (2) an error information register that captures and stores error information for host system analysis. This segmentation allows each component to specialize in its specific function, reducing overall complexity while improving error detection capability. The ECC logic focuses on correction while the register handles information reporting.
3Measurement precision
If error counting and monitoring is implemented, then error tracking accuracy is improved, but device complexity increases
Solution Approach 1:
The memory device performs error monitoring and counting autonomously through its on-die ECC logic and integrated error information register. The ECC logic automatically detects errors, corrects them, and simultaneously populates the error information register with relevant data without requiring external intervention. This self-service approach improves error tracking accuracy while minimizing the added complexity, as the monitoring functions are built into the existing memory device architecture rather than requiring separate external monitoring components.
Data Source
AI summary
An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.