Memory ECS Priority Control for Read Error Scrubbing
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Solution Overview
Problem
As data transmission speeds increase in semiconductor devices, the likelihood of errors during data transmission also rises, necessitating reliable methods to ensure data integrity, particularly through error check scrub (ECS) operations.
Innovation Solution
A semiconductor system that latches a command address when an error occurs during a read operation, performs an ECS operation on the corresponding memory cell, and then sequentially corrects errors in multiple memory cells based on priority determined by latch row and column addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve operating speed, then productivity is improved, but reliability deteriorates due to increased error probability
Solution Approach 1:
The patent implements preliminary error detection by continuously monitoring data integrity during transmission and performing error check scrub operations before errors propagate. The system proactively identifies potential errors in memory cells and corrects them preemptively, rather than waiting for errors to manifest during data retrieval.
Solution Approach 2:
The patent employs feedback mechanisms where error detection results trigger automatic error check scrub operations. The system monitors data integrity status and adjusts its operation accordingly - when errors are detected, the system initiates corrective ECS operations on affected memory cells, creating a closed-loop error management system that adapts to real-time conditions.
2Reliability
If error check scrub operation is performed on all memory cells sequentially, then reliability is improved, but loss of time increases due to sequential processing
Solution Approach 1:
The patent divides the error check scrub operation into segments based on memory cell priority levels. Instead of processing all memory cells uniformly, the system segments them into different priority groups and processes high-priority cells first. This segmentation allows critical error corrections to be performed immediately while lower-priority cells are handled subsequently, reducing overall time loss.
Solution Approach 2:
The patent implements dynamic priority assignment for memory cells based on their error status and operational criticality. The system can adjust the priority of different memory cells dynamically, allowing it to adapt to changing conditions and focus computational resources on the most critical error corrections first, thereby minimizing the impact on system performance.
3Reliability
If error check scrub operation is prioritized for specific memory cells, then reliability is improved for critical data, but device complexity increases due to priority management
Solution Approach 1:
The patent applies local quality by assigning different priority levels to different memory cells or memory regions based on their specific characteristics and importance. Rather than treating all memory cells uniformly, the system identifies specific cells that require higher priority error correction and applies enhanced error check scrub operations only to those locations, optimizing reliability for critical data while managing complexity through targeted rather than universal processing.
Data Source
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AI summary
A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.