Memory EDC Interface Using DM Lines for Bus Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in effectively detecting and correcting errors during data transmission between memory components and controllers, particularly due to limitations in carrying error detection and correction (EDC) bits, especially when using Hamming codes that require more bits than available in a single data unit.
Innovation Solution
The memory system generates and stores EDC bits internally and uses command/address signal lines to supplement the data signal lines, allowing for masked writes where check bits are sent coincident with an asserted data mask signal, ensuring error detection and correction across the communication interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Hamming codes are used for error detection and correction, then error correction capability is improved, but the number of bits required exceeds the capacity of a single data unit
Solution Approach 1:
The patent divides the transmission process into multiple segments: data units are transmitted in bursts, and EDC bits are transmitted separately in subsequent bursts. This segmentation allows the system to use Hamming codes (requiring more bits) without overwhelming the data unit capacity, as EDC bits are carried in dedicated transmission slots rather than being embedded within single data units.
Solution Approach 2:
The patent transitions from a single-dimension approach (embedding all EDC bits within one data unit) to a multi-dimensional approach by utilizing multiple transmission bursts and different signal line groups. EDC bits are transmitted in a second burst using the same data signal lines, effectively adding a temporal dimension to the bit transmission capacity.
2Reliability
If dedicated signal lines are used for EDC bits, then error detection reliability is improved, but device complexity increases
Solution Approach 1:
The patent makes the data signal lines universal by using them for both data transmission and EDC bit transmission at different times. The same physical lines carry data during the first burst and EDC bits during the second burst, eliminating the need for separate dedicated EDC signal lines while maintaining error detection reliability.
Solution Approach 2:
The patent merges the data transmission function and EDC bit transmission function into a single set of signal lines. By time-division multiplexing these lines, the system combines what would traditionally require separate physical channels into one shared medium, reducing overall device complexity.
3Reliability
If check bits are sent on data mask signal lines, then error detection capability is improved, but the data mask functionality is compromised
Solution Approach 1:
The patent employs periodic action by alternating the function of signal lines between bursts. Data mask lines carry mask signals during data bursts and EDC bits during EDC bursts, with clear periodic separation. This timing-based differentiation ensures that when EDC bits are transmitted, the data mask function is temporarily suspended, but this is acceptable because no data transmission occurs during EDC bit transmission periods.
Data Source
AI summary
A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.